/**
  * @brief  Enters STANDBY mode.
  * @param  None
  * @retval None
  */
void PWR_EnterSTANDBYMode(void) {
    /* Clear Wake-up flag */
    PWR->CR |= CR_CWUF_Set;
    /* Select STANDBY mode */
    PWR->CR |= CR_PDDS_Set;
    /* Set SLEEPDEEP bit of Cortex System Control Register */
    *(__IO uint32_t*)SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* This option is used to ensure that store operations are completed */
#if defined(__CC_ARM)
    __force_stores();
#endif
    /* Request Wait For Interrupt */
    __WFI();
}
Beispiel #2
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/**
  * @brief Enters Standby mode.
  * @note In Standby mode, all I/O pins are high impedance except for:
  *          - Reset pad (still available) 
  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
  *            Alarm out, or RTC clock calibration out.
  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
  *          - WKUP pins if enabled.       
  * @retval None
  */
void HAL_PWR_EnterSTANDBYMode(void)
{
  /* Select Standby mode */
  PWR->CR1 |= PWR_CR1_PDDS;
  
  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  
  /* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
  __force_stores();
#endif
  /* Request Wait For Interrupt */
  __WFI();
}
Beispiel #3
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/**
  * @brief Enter Standby mode.
  * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched 
  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
  *        in which case the regulator is in low-power mode. 
  *        SRAM1 and register contents are lost except for registers in the Backup domain and 
  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
  *        to set RRS bit.   
  *        The BOR is available.  
  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
  *        same.
  *        These states are effective in Standby mode only if APC bit is set through
  *        HAL_PWREx_EnablePullUpPullDownConfig() API.        
  * @retval None
  */
void HAL_PWR_EnterSTANDBYMode(void)
{
  /* Set Stand-by mode */
  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);

  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
  __force_stores();
#endif
  /* Request Wait For Interrupt */
  __WFI();
}
Beispiel #4
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/**
  * @brief  Enter the system to STANDBY mode.
  * @note   The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
  * @note   When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
  *         the HSI RC oscillator is selected as system clock.
  * @retval None.
  */
void HAL_PWR_EnterSTANDBYMode(void)
{
  /* Keep DSTANDBY mode when D1 domain enters Deepsleep */
  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);

  /* Keep DSTANDBY mode when D2 domain enters Deepsleep */
  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);

  /* Keep DSTANDBY mode when D3 domain enters Deepsleep */
  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);

  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

  /* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
  __force_stores();
#endif
  /* Request Wait For Interrupt */
  __WFI();
}