Beispiel #1
0
static void
__hal_ring_rxdblock_link(xge_hal_mempool_h mempoolh,
                         xge_hal_ring_t *ring, int from, int to)
{
    xge_hal_ring_block_t *to_item, *from_item;
    dma_addr_t to_dma, from_dma;
    pci_dma_h to_dma_handle, from_dma_handle;

    /* get "from" RxD block */
    from_item = (xge_hal_ring_block_t *)
                __hal_mempool_item((xge_hal_mempool_t *) mempoolh, from);
    xge_assert(from_item);

    /* get "to" RxD block */
    to_item = (xge_hal_ring_block_t *)
              __hal_mempool_item((xge_hal_mempool_t *) mempoolh, to);
    xge_assert(to_item);

    /* return address of the beginning of previous RxD block */
    to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle);

    /* set next pointer for this RxD block to point on
     * previous item's DMA start address */
    __hal_ring_block_next_pointer_set(from_item, to_dma);

    /* return "from" RxD block's DMA start address */
    from_dma =
        __hal_ring_item_dma_addr(mempoolh, from_item, &from_dma_handle);

#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
    /* we must sync "from" RxD block, so hardware will see it */
    xge_os_dma_sync(ring->channel.pdev,
                    from_dma_handle,
                    from_dma + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
                    __hal_ring_item_dma_offset(mempoolh, from_item) +
                    XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
                    sizeof(u64),
                    XGE_OS_DMA_DIR_TODEVICE);
#endif

    xge_debug_ring(XGE_TRACE, "block%d:0x"XGE_OS_LLXFMT" => block%d:0x"XGE_OS_LLXFMT,
                   from, (unsigned long long)from_dma, to,
                   (unsigned long long)to_dma);
}
Beispiel #2
0
void
__hal_ring_prc_enable(xge_hal_channel_h channelh)
{
	xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh;
	xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh;
	xge_hal_pci_bar0_t *bar0;
	u64 val64;
	void *first_block;
	int block_num;
	xge_hal_ring_queue_t *queue;
	pci_dma_h dma_handle;

	xge_assert(ring);
	xge_assert(ring->channel.pdev);
	bar0 = (xge_hal_pci_bar0_t *) (void *)
			((xge_hal_device_t *)ring->channel.devh)->bar0;

	queue = &ring->config->queue[ring->channel.post_qid];
	xge_assert(queue->buffer_mode == 1 ||
		    queue->buffer_mode == 3 ||
		    queue->buffer_mode == 5);

	/* last block in fact becomes first. This is just the way it
	 * is filled up and linked by item_alloc() */

	block_num = queue->initial;
	first_block = __hal_mempool_item(ring->mempool, block_num - 1);
	val64 = __hal_ring_item_dma_addr(ring->mempool,
					 first_block, &dma_handle);
	xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
			val64, &bar0->prc_rxd0_n[ring->channel.post_qid]);

	xge_debug_ring(XGE_TRACE, "ring%d PRC DMA addr 0x%llx initialized",
			ring->channel.post_qid, (unsigned long long)val64);

	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
		ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]);
	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC &&
	    !queue->rth_en) {
		val64 |= XGE_HAL_PRC_CTRL_RTH_DISABLE;
	}
	val64 |= XGE_HAL_PRC_CTRL_RC_ENABLED;

	val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
	val64 &= ~XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
	val64 |= XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(
		(hldev->config.pci_freq_mherz * queue->backoff_interval_us));

	/* Beware: no snoop by the bridge if (no_snoop_bits) */
	val64 |= XGE_HAL_PRC_CTRL_NO_SNOOP(queue->no_snoop_bits);

        /* Herc: always use group_reads */
	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
	        val64 |= XGE_HAL_PRC_CTRL_GROUP_READS;

	xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
			val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);

	/* Configure Receive Protocol Assist */
	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
			ring->channel.regh0, &bar0->rx_pa_cfg);
	val64 |= XGE_HAL_RX_PA_CFG_SCATTER_MODE(ring->config->scatter_mode);
	val64 |= (XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI | XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL);
	/* Clean STRIP_VLAN_TAG bit and set as config from upper layer */
	val64 &= ~XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(1);
	val64 |= XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(ring->config->strip_vlan_tag);

	xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
			val64, &bar0->rx_pa_cfg);

	xge_debug_ring(XGE_TRACE, "ring%d enabled in buffer_mode %d",
			ring->channel.post_qid, queue->buffer_mode);
}
Beispiel #3
0
/*
 * __hal_ring_rxdblock_link - Link the RxD blocks
 * @mempoolh: Handle to the memory pool of the ring
 * @ring: ring
 * @from: RxD block from which to link
 * @to: RxD block to which to link to
 *
 * This function returns the dma address of a given item
 */
static void
__hal_ring_rxdblock_link(
    vxge_hal_mempool_h mempoolh,
    __hal_ring_t *ring,
    u32 from,
    u32 to)
{
	vxge_hal_ring_block_t *to_item, *from_item;
	dma_addr_t to_dma, from_dma;
	pci_dma_h to_dma_handle, from_dma_handle;
	__hal_device_t *hldev;

	vxge_assert((mempoolh != NULL) && (ring != NULL));

	hldev = (__hal_device_t *) ring->channel.devh;

	vxge_hal_trace_log_ring("==> %s:%s:%d",
	    __FILE__, __func__, __LINE__);

	vxge_hal_trace_log_ring(
	    "mempoolh = 0x"VXGE_OS_STXFMT", ring = 0x"VXGE_OS_STXFMT", "
	    "from = %d, to = %d", (ptr_t) mempoolh, (ptr_t) ring, from, to);

	/* get "from" RxD block */
	from_item = (vxge_hal_ring_block_t *) __hal_mempool_item(
	    (vxge_hal_mempool_t *) mempoolh, from);
	vxge_assert(from_item);

	/* get "to" RxD block */
	to_item = (vxge_hal_ring_block_t *) __hal_mempool_item(
	    (vxge_hal_mempool_t *) mempoolh, to);
	vxge_assert(to_item);

	/* return address of the beginning of previous RxD block */
	to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle);

	/*
	 * set next pointer for this RxD block to point on
	 * previous item's DMA start address
	 */
	__hal_ring_block_next_pointer_set(from_item, to_dma);

	/* return "from" RxD block's DMA start address */
	from_dma = __hal_ring_item_dma_addr(
	    mempoolh, from_item, &from_dma_handle);

#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
	/* we must sync "from" RxD block, so hardware will see it */
	vxge_os_dma_sync(ring->channel.pdev,
	    from_dma_handle,
	    from_dma + VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
	    __hal_ring_item_dma_offset(mempoolh, from_item) +
	    VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
	    sizeof(u64),
	    VXGE_OS_DMA_DIR_TODEVICE);
#endif

	vxge_hal_info_log_ring(
	    "block%d:0x"VXGE_OS_STXFMT" => block%d:0x"VXGE_OS_STXFMT,
	    from, (ptr_t) from_dma, to, (ptr_t) to_dma);

	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
	    __FILE__, __func__, __LINE__);

}