static void i2s_codec_init(void)
{
__cpm_start_aic1();
__cpm_start_aic2();
__aic_enable();
__i2s_internal_codec();
__i2s_as_slave();
__i2s_select_i2s();
__aic_select_i2s();
__aic_disable_byteswap();
__aic_disable_unsignadj();
__aic_disable_mono2stereo();
i2s_codec_reset();
REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_44)
| ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_0));
mdelay(15);
REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVR | ICDC_CDCCR1_VRCGL | ICDC_CDCCR1_VRCGH);
REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG);
mdelay(600);
REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_HPCG | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP);
mdelay(2);
/* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */
REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EADC |
ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_HPMUTE)) | (ICDC_CDCCR1_EDAC
| ICDC_CDCCR1_SW2ON);
HP_on_off_flag = 1; /* HP is on */
}
////////////////////////////////////////////////////
// 功能: 开打声音设备
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
void MediaSysInit()
{
// Start AIC and DMA Clock
// Clock gate Bits. Controls the clock supplies to some peripherals. If set,
// clock supplies to associated devices are stopped, and registers of the
// device cannot be accessed also
//CLRREG32(A_CPM_CLKGR, CLKGR_STOP_AIC_PCLK | CLKGR_STOP_DMAC);
__cpm_start_aic1(); //clear CPM_CLKGR_AIC1
__cpm_start_aic2(); //clear CPM_CLKGR_AIC2
__cpm_start_dmac(); //clear CPM_CLKGR_DMAC
// I2S device clock divider Register (I2SCDR) is a 32-bit read/write register that specifies the divider of
// I2S device clock . This register is initialized to 0x00000004 only by any reset. Only word access can
// be used on I2SCDR
//OUTREG32(A_CPM_I2SCDR, 0x00);
REG_CPM_I2SCDR = 0x00;
// change enable. If CE is 1, writes on CDIV, HDIV, PDIV, MDIV, UDIV,
// PXDIV or LDIV will start a frequency changing sequence immediately.
// When CE is 0, writes on CDIV, HDIV, PDIV, MDIV, UDIV, PXDIV and
// LDIV will not start a frequency changing sequence immediately. The
// division ratio is actually updated in PLL multiple ratio changing sequence
// or PLL Disable Sequence.
// 0: Division ratios are updated in PLL multiple ratio changing sequence or
// PLL Disable Sequence
// 1: Division ratios are updated immediately
//SETREG32(A_CPM_CPCCR, CPCCR_CHANGE_EN);
__cpm_enable_pll_change();
// I2SCR contains bits to control BIT_CLK stop, audio sample size, I2S or MSB-justified selection in
// I2S/MSB-justified. It is valid only in I2S/MSB-justified format.
//OUTREG32(A_AIC_I2SCR, 0x00);
REG_AIC_I2SCR = 0;
// AIC Init
// AICFR contains bits to control FIFO threshold, AC-link or I2S/MSB-justified selection, AIC reset,
// master/slave selection, and AIC enable.
// Play ZERO sample when TX FIFO underflow or Play last sample when TX FIFO underflow
REG_AIC_FR = AIC_FR_LSMP;
// Internal CODEC
//OUTREG32(A_AIC_AICFR, AICFR_CODEC_INT | AICFR_LSMP_LAST_SAMPLE);
__aic_internal_codec();
// 0 Select AC-link format
// 1 Select I2S/MSB-justified format
//SETREG32(A_AIC_AICFR, AICFR_I2S);
__aic_select_i2s();
//Enable SYSCLK output. When this bit is 1, the SYSCLK outputs to chip
//outside is enabled. Else, the clock is disabled.
__i2s_select_i2s(); // OUTREG32(A_AIC_I2SCR, I2SCR_I2S);
// SETREG32(A_AIC_AICFR, AICFR_BCKD_IN | AICFR_SYNCD_IN);
__i2s_as_slave();
// SETREG32(A_AIC_AICFR, AICFR_ENABLE);
__aic_enable();
// AIC Configure
//SETREG32(A_AIC_AICFR, AICFR_RFTH(16) | AICFR_TFTH(24));
// Receive FIFO threshold for interrupt or DMA request. The RFTH valid
// value is 0 ~ 15
__i2s_set_receive_trigger((16/2) - 1);
// Transmit FIFO threshold for interrupt or DMA request
__i2s_set_transmit_trigger(24/2);
//OUTREG32(A_AIC_AICCR, AICCR_OSS_16BIT | AICCR_ISS_16BIT);
// Output Sample Size. These bits reflect output sample data size from
// memory or register. The data sizes supported are: 8, 16, 18, 20 and 24
// bits. The sample data is LSB-justified in memory/register
__i2s_set_oss_sample_size(16);
// Input Sample Size. These bits reflect input sample data size to memory or
// register. The data sizes supported are: 8, 16, 18, 20 and 24 bits. The
// sample data is LSB-justified in memory/register.
__i2s_set_iss_sample_size(16);
//SETREG32(A_AIC_AICCR, AICCR_RDMS | AICCR_TDMS | AICCR_FLUSH_FIFO);
// Transmit DMA enable. This bit is used to enable or disable the DMA
// during transmit audio data
__i2s_enable_transmit_dma();
// Receive DMA enable. This bit is used to enable or disable the DMA during
// receiving audio data
__i2s_enable_receive_dma();
//SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO);
// JZ4750 D8 == FIFO Flush. Write 1 to this bit flush transmit/receive FIFOs to empty.Writing 0 to this bit has no effect and this bit is always reading 0.
// JZ4755 D7 == Receive FIFO Flush. Write 1 to this bit flush receive FIFOs to empty
// D8 == Transmit FIFO Flush. Write 1 to this bit flush transmit FIFOs to empty.
// __aic_flush_fifo();
REG_AIC_CR |= (1<<7);
// I2SCR contains bits to control BIT_CLK stop, audio sample size, I2S or MSB-justified selection in
// I2S/MSB-justified. It is valid only in I2S/MSB-justified format.
OUTREG32(A_AIC_AICSR, 0x00000000);
//CLRREG32(A_AIC_AICFR, AICFR_LSMP_LAST_SAMPLE);
__aic_clr_esclk();
#ifdef KPRINTF_DEF
kprintf("AICFR[0x%x]\n", INREG32(AIC_FR));
kprintf("AICCR[0x%x]\n", INREG32(AIC_CR));
kprintf("AICSR[0x%x]\n", INREG32(AIC_SR));
#endif
fDeviceStatus = DEVICE_CLOSE_STATUS;
OpenMediaCodecDevice();
}
