externC void _mb93091_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val) { cyg_uint32 cfg_addr, addr, status; if (!_mb93091_has_vdk) return; #ifdef CYGPKG_IO_PCI_DEBUG diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val); #endif // CYGPKG_IO_PCI_DEBUG if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) { // PCI bridge addr = _MB93091_PCI_CONFIG + (offset << 1); } else { cfg_addr = _cfg_addr(bus, devfn, offset); HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr); addr = _MB93091_PCI_CONFIG_DATA; } HAL_WRITE_UINT32(addr, cfg_val); HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status); if (status & _MB93091_PCI_STAT_ERROR_MASK) { // Cycle failed - clean up and get out HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK); } HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0); }
externC cyg_uint16 _mb93091_pci_cfg_read_uint16(int bus, int devfn, int offset) { cyg_uint32 cfg_addr, addr, status; cyg_uint16 cfg_val = (cyg_uint16)0xFFFF; if (!_mb93091_has_vdk) return cfg_val; #ifdef CYGPKG_IO_PCI_DEBUG diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset); #endif // CYGPKG_IO_PCI_DEBUG if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) { // PCI bridge addr = _MB93091_PCI_CONFIG + ((offset << 1) ^ 0x02); } else { cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02); HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr); addr = _MB93091_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02); } HAL_READ_UINT16(addr, cfg_val); HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status); if (status & _MB93091_PCI_STAT_ERROR_MASK) { // Cycle failed - clean up and get out cfg_val = (cyg_uint16)0xFFFF; HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK); } #ifdef CYGPKG_IO_PCI_DEBUG diag_printf("%x\n", cfg_val); #endif // CYGPKG_IO_PCI_DEBUG HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0); return cfg_val; }
externC void hal_ppc405_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val) { cyg_uint32 cfg_addr; #ifdef CYGPKG_IO_PCI_DEBUG diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val); #endif // CYGPKG_IO_PCI_DEBUG cfg_addr = _cfg_addr(bus, devfn, offset); HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr); HAL_WRITE_UINT32LE(PCIC0_CFGDATA, cfg_val); }
externC cyg_uint32 hal_ppc405_pci_cfg_read_uint32(int bus, int devfn, int offset) { cyg_uint32 cfg_addr; cyg_uint32 cfg_val = (cyg_uint32) 0xFFFFFFFF; #ifdef CYGPKG_IO_PCI_DEBUG diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset); #endif // CYGPKG_IO_PCI_DEBUG cfg_addr = _cfg_addr(bus, devfn, offset); HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr); HAL_READ_UINT32LE(PCIC0_CFGDATA, cfg_val); #ifdef CYGPKG_IO_PCI_DEBUG diag_printf("%x\n", cfg_val); #endif // CYGPKG_IO_PCI_DEBUG return cfg_val; }