/*!
* ======== IntXbar_connect ========
*/
Void IntXbar_connect(UInt xbarInstance, UInt intSource)
{
UInt32 regOffset;
UInt32 *intXbarReg;
UInt16 intXbarLength;
#ifdef xdc_target__isaCompatible_arp32
UInt32 cpuId = _get_cpunum();
if (cpuId == 0) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE0);
}
else if (cpuId == 1) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE1);
}
else if (cpuId == 2) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE2);
}
else if (cpuId == 3) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE3);
}
intXbarLength = IntXbar_NUM_EVE_XBAR_INST;
Assert_isTrue((xbarInstance <= intXbarLength) && (xbarInstance >= 1),
IntXbar_A_badEveXbarInstanceNum);
#elif defined xdc_target__isaCompatible_66
extern cregister volatile UInt DNUM;
if (DNUM) { /* DSP1 */
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_DSP1);
}
else { /* DSP0 */
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_DSP0);
}
intXbarLength = IntXbar_NUM_DSP_XBAR_INST;
Assert_isTrue((xbarInstance <= intXbarLength) && (xbarInstance >= 1),
IntXbar_A_badDspXbarInstanceNum);
#elif (defined xdc_target__isaCompatible_v7M || \
defined xdc_target__isaCompatible_v7M4)
if (*(UInt *)(PID0_ADDRESS)) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_BENELLI_CORE1);
}
else {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_BENELLI_CORE0);
}
intXbarLength = IntXbar_NUM_BENELLI_XBAR_INST;
Assert_isTrue((xbarInstance <= intXbarLength) && (xbarInstance >= 1),
IntXbar_A_badBenelliXbarInstanceNum);
#elif defined xdc_target__isaCompatible_v7A15
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_A15);
intXbarLength = IntXbar_NUM_A15_XBAR_INST;
Assert_isTrue((xbarInstance <= intXbarLength) && (xbarInstance >= 1),
IntXbar_A_badA15XbarInstanceNum);
#endif
Assert_isTrue((intSource <= 391), IntXbar_A_badIntSourceIdx);
regOffset = (xbarInstance - 1) / 2;
if ((xbarInstance - 1) % 2) {
intXbarReg[regOffset] = (intXbarReg[regOffset] & 0x0000FFFF) |
(intSource << 16);
}
else {
intXbarReg[regOffset] = (intXbarReg[regOffset] & 0xFFFF0000) |
(intSource);
}
IntXbar_module->intXbar[xbarInstance - 1] = intSource;
}
/*!
* ======== IntXbar_initIntXbar ========
*/
Void IntXbar_initIntXbar()
{
UInt intNum;
UInt32 regOffset;
UInt32 *intXbarReg;
UInt16 intXbarLength;
#ifdef xdc_target__isaCompatible_arp32
UInt32 cpuId = _get_cpunum();
if (cpuId == 0) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE0);
}
else if (cpuId == 1) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE1);
}
else if (cpuId == 2) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE2);
}
else if (cpuId == 3) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_EVE3);
}
intXbarLength = IntXbar_NUM_EVE_XBAR_INST;
#elif defined xdc_target__isaCompatible_66
extern cregister volatile UInt DNUM;
if (DNUM) { /* DSP1 */
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_DSP1);
}
else { /* DSP0 */
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_DSP0);
}
intXbarLength = IntXbar_NUM_DSP_XBAR_INST;
#elif (defined xdc_target__isaCompatible_v7M || \
defined xdc_target__isaCompatible_v7M4)
if (*(UInt *)(PID0_ADDRESS)) {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_BENELLI_CORE1);
}
else {
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_BENELLI_CORE0);
}
intXbarLength = IntXbar_NUM_BENELLI_XBAR_INST;
#elif defined xdc_target__isaCompatible_v7A15
intXbarReg = (UInt32 *)(IntXbar_MMR_BASE_ADDR +
IntXbar_MMR_OFFSET_A15);
#endif
for (intNum = 0; intNum < intXbarLength; intNum++) {
if (IntXbar_module->intXbar[intNum]) {
regOffset = intNum / 2;
if (intNum % 2) {
intXbarReg[regOffset] = (intXbarReg[regOffset] & 0x0000FFFF) |
(IntXbar_module->intXbar[intNum] << 16);
}
else {
intXbarReg[regOffset] = (intXbarReg[regOffset] & 0xFFFF0000) |
(IntXbar_module->intXbar[intNum]);
}
}
}
}
/*!
* ======== IntXbar_initXbarRegs ========
*/
Void IntXbar_initXbarRegs(volatile UInt32 **intXbarReg, UInt16 *intXbarLength)
{
#ifdef xdc_target__isaCompatible_arp32
UInt32 cpuId = _get_cpunum();
#elif defined xdc_target__isaCompatible_66
extern cregister volatile UInt DNUM;
#endif
#ifdef xdc_target__isaCompatible_arp32
Assert_isTrue((cpuId <= 3), IntXbar_A_badEveCpuId);
if (cpuId == 0) {
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_EVE0);
}
else if (cpuId == 1) {
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_EVE1);
}
else if (cpuId == 2) {
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_EVE2);
}
else {
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_EVE3);
}
*intXbarLength = IntXbar_NUM_EVE_XBAR_INST;
#elif defined xdc_target__isaCompatible_66
Assert_isTrue((DNUM == 0) || (DNUM == 1),
IntXbar_A_badDspCpuId);
if (DNUM) { /* DSP1 */
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_DSP1);
}
else { /* DSP0 */
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_DSP0);
}
*intXbarLength = IntXbar_NUM_DSP_XBAR_INST;
#elif (defined xdc_target__isaCompatible_v7M4)
Assert_isTrue((Core_getIpuId() == 1) || (Core_getIpuId() == 2),
IntXbar_A_badBenelliIpuId);
if (Core_getIpuId() == 1) {
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_BENELLI_IPU1);
}
else {
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_BENELLI_IPU2);
}
*intXbarLength = IntXbar_NUM_BENELLI_XBAR_INST;
#elif defined xdc_target__isaCompatible_v7A15
*intXbarReg = (UInt32 *)(IntXbar_mmrBaseAddr +
IntXbar_MMR_OFFSET_A15);
*intXbarLength = IntXbar_NUM_A15_XBAR_INST;
#endif
}