void init_m3_state_machine(void)
{
int i = 0;
/* Flush out NVIC interrupts */
for (i=0; i<AM335X_NUM_EXT_INTERRUPTS; i++)
{
nvic_disable_irq(i);
nvic_clear_irq(i);
}
msg_init();
trace_init();
pm_init();
/* Enable only the MBX IRQ */
nvic_enable_irq(AM335X_IRQ_MBINT0);
/*
* In the remote case where we disabled the MPU CLOCK
* enable it again, no harm in writing to the reg
* even if this was not needed
*/
mpu_enable();
a8_notify(CMD_STAT_PASS);
}
/* If only notification is needed, use the a8_notify() API */
void a8_m3_low_power_sync(int cmd_stat_value)
{
/* Disable this part for now */
a8_notify(cmd_stat_value);
/* Enable the PRCM interrupt for MPU gated state */
nvic_enable_irq(AM335X_IRQ_PRCM_M3_IRQ2);
}
int am335_init(void)
{
int i;
/*
* Each interrupt has a priority register associated with it
* 8 bits... only 7:6:5:4 are available for SA
* out of the 16 levels here... using a priority grouping
* these 4 bits can be further split into preempt priority
* and subpriority fields
*/
scr_enable_sleepdeep();
scr_enable_sleeponexit();
/* Disable all the external interrupts */
for (i=0; i < CM3_NUM_EXT_INTERRUPTS; i++)
nvic_disable_irq(i);
/* Disable Tamper swakeup, a new addition for AM43XX SOCs */
if (soc_id == AM43XX_SOC_ID)
nvic_disable_irq(CM3_IRQ_TPM_WAKE);
/* Clean the IPC registers */
m3_param_reset();
trace_init();
pm_reset();
setup_soc();
/* Enable only the MBX IRQ */
nvic_enable_irq(CM3_IRQ_MBINT0);
nvic_enable_irq(53);
m3_firmware_version();
/* TODO: Enable PRCM_INT2 with a dummy handler */
/* Notify A8 of init completion */
a8_notify(CMD_STAT_PASS);
/* Ok we are done here */
return 0;
}
