/*
* routine to add vcl to one net/reg/var/event
*/
static void add_vcl(handle net)
{
int typ, fulltyp;
char s1[1024];
/* DBG remove -- */
typ = acc_fetch_type(net);
fulltyp = acc_fetch_fulltype(net);
if (typ != accTerminal) strcpy(s1, acc_fetch_fullname(net));
else strcpy(s1, "**terminal**");
io_printf("Adding vcl for %s type %s (fulltype %s)\n", s1,
acc_fetch_type_str(typ), acc_fetch_type_str(fulltyp));
/* --- */
if (typ == accNet)
{
acc_vcl_add(net, wire_prt_vclchg, (void *) net, vcl_verilog_strength);
}
else acc_vcl_add(net, var_prt_vclchg, (void *) net, vcl_verilog_logic);
}
/*************************************************
lxt2_add
- add object to file
************************************************/
static void lxt2_add( handle object, int depth )
{
int real = 0;
int event = 0;
int flags;
int msb;
int lsb;
info_p info;
handle block;
handle term;
static int filter[] = {
accIntegerVar,
accNamedEvent,
accNet,
accRealVar,
accRegister,
accTimeVar,
0
};
switch( acc_fetch_type(object) ) {
case accNamedEvent:
flags = LXT2_WR_SYM_F_BITS;
event = 1;
break;
case accRealVar:
flags = LXT2_WR_SYM_F_DOUBLE;
real = 1;
break;
case accIntegerVar:
case accNet:
case accPort:
case accReg:
case accTimeVar:
case accParameter:
flags = LXT2_WR_SYM_F_BITS;
break;
case accStatement:
case accTask:
case accModule:
term = null;
while(1) {
term = acc_next( filter, object, term );
if( term == null ) {
break;
}
lxt2_add( term, depth );
}
if( depth == 1 ) {
return;
}
block = null;
while(1) {
block = acc_next_child( object, block );
if( block == null ) {
break;
}
lxt2_add( block, (depth==0) ? 0 : depth-1 );
}
return;
default:
return;
}
info = (info_p)malloc( sizeof(info_t) );
if( !info ) {
tf_error( "cannot allocate memory" );
tf_dofinish();
return;
}
info->object = object;
info->name = strdup( acc_fetch_fullname(object) );
info->next = lxt.objectList;
lxt.objectList = info;
info->sequence = lxt.sequence;
info->event = event;
info->real = real;
info->updateNext = 0;
if( real ) {
info->symbol = lxt2_wr_symbol_add( lxt.t, info->name, 0, 0, 0, flags );
} else if( event ) {
info->symbol = lxt2_wr_symbol_add( lxt.t, info->name, 0, 0, 0, flags );
} else {
acc_fetch_range( object, &msb, &lsb );
#if DEBUG
io_printf( "lxt2_add: %s [ %d : %d ]\n",
info->name, msb, lsb );
#endif
info->symbol = lxt2_wr_symbol_add( lxt.t, info->name, 0, msb, lsb, flags );
}
acc_vcl_add( object, lxt2_changed, (char*)info, vcl_verilog_logic );
#if DEBUG
io_printf( "lxt2_recordvars: adding %p %s\n", info->symbol, info->name );
#endif
}
