static int
snd_ad1889_capture_prepare(struct snd_pcm_substream *ss)
{
struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
struct snd_pcm_runtime *rt = ss->runtime;
unsigned int size = snd_pcm_lib_buffer_bytes(ss);
unsigned int count = snd_pcm_lib_period_bytes(ss);
u16 reg;
ad1889_channel_reset(chip, AD_CHAN_ADC);
reg = ad1889_readw(chip, AD_DS_RAMC);
/* Mask out 16-bit / Stereo */
reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST);
if (snd_pcm_format_width(rt->format) == 16)
reg |= AD_DS_RAMC_AD16;
if (rt->channels > 1)
reg |= AD_DS_RAMC_ADST;
/* let's make sure we don't clobber ourselves */
spin_lock_irq(&chip->lock);
chip->ramc.size = size;
chip->ramc.reg = reg;
chip->ramc.addr = rt->dma_addr;
ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg);
/* Set up DMA */
ad1889_load_adc_buffer_address(chip, chip->ramc.addr);
ad1889_load_adc_buffer_count(chip, size);
ad1889_load_adc_interrupt_count(chip, count);
/* writes flush */
ad1889_readw(chip, AD_DS_RAMC);
spin_unlock_irq(&chip->lock);
ad1889_debug("prepare capture: addr = 0x%x, count = %u, "
"size = %u, reg = 0x%x, rate = %u\n", chip->ramc.addr,
count, size, reg, rt->rate);
return 0;
}
static void
ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
{
u16 reg;
if (channel & AD_CHAN_WAV) {
/* Disable wave channel */
reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
ad1889_writew(chip, AD_DS_WSMC, reg);
chip->wave.reg = reg;
/* disable IRQs */
reg = ad1889_readw(chip, AD_DMA_WAV);
reg &= AD_DMA_IM_DIS;
reg &= ~AD_DMA_LOOP;
ad1889_writew(chip, AD_DMA_WAV, reg);
/* clear IRQ and address counters and pointers */
ad1889_load_wave_buffer_address(chip, 0x0);
ad1889_load_wave_buffer_count(chip, 0x0);
ad1889_load_wave_interrupt_count(chip, 0x0);
/* flush */
ad1889_readw(chip, AD_DMA_WAV);
}
if (channel & AD_CHAN_ADC) {
/* Disable ADC channel */
reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
ad1889_writew(chip, AD_DS_RAMC, reg);
chip->ramc.reg = reg;
reg = ad1889_readw(chip, AD_DMA_ADC);
reg &= AD_DMA_IM_DIS;
reg &= ~AD_DMA_LOOP;
ad1889_writew(chip, AD_DMA_ADC, reg);
ad1889_load_adc_buffer_address(chip, 0x0);
ad1889_load_adc_buffer_count(chip, 0x0);
ad1889_load_adc_interrupt_count(chip, 0x0);
/* flush */
ad1889_readw(chip, AD_DMA_ADC);
}
}
static void
ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
{
u16 reg;
if (channel & AD_CHAN_WAV) {
reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
ad1889_writew(chip, AD_DS_WSMC, reg);
chip->wave.reg = reg;
reg = ad1889_readw(chip, AD_DMA_WAV);
reg &= AD_DMA_IM_DIS;
reg &= ~AD_DMA_LOOP;
ad1889_writew(chip, AD_DMA_WAV, reg);
ad1889_load_wave_buffer_address(chip, 0x0);
ad1889_load_wave_buffer_count(chip, 0x0);
ad1889_load_wave_interrupt_count(chip, 0x0);
ad1889_readw(chip, AD_DMA_WAV);
}
if (channel & AD_CHAN_ADC) {
reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
ad1889_writew(chip, AD_DS_RAMC, reg);
chip->ramc.reg = reg;
reg = ad1889_readw(chip, AD_DMA_ADC);
reg &= AD_DMA_IM_DIS;
reg &= ~AD_DMA_LOOP;
ad1889_writew(chip, AD_DMA_ADC, reg);
ad1889_load_adc_buffer_address(chip, 0x0);
ad1889_load_adc_buffer_count(chip, 0x0);
ad1889_load_adc_interrupt_count(chip, 0x0);
ad1889_readw(chip, AD_DMA_ADC);
}
}