static void
show_adapter_info(void)
{
struct video_adapter_info ad;
ad.va_index = 0;
if (ioctl(0, CONS_ADPINFO, &ad) == -1) {
revert();
errc(1, errno, "obtaining adapter information");
}
printf("fb%d:\n", ad.va_index);
printf(" %.*s%d, type:%s%s (%d), flags:0x%x\n",
(int)sizeof(ad.va_name), ad.va_name, ad.va_unit,
(ad.va_flags & V_ADP_VESA) ? "VESA " : "",
adapter_name(ad.va_type), ad.va_type, ad.va_flags);
printf(" initial mode:%d, current mode:%d, BIOS mode:%d\n",
ad.va_initial_mode, ad.va_mode, ad.va_initial_bios_mode);
printf(" frame buffer window:0x%x, buffer size:0x%zx\n",
ad.va_window, ad.va_buffer_size);
printf(" window size:0x%zx, origin:0x%x\n",
ad.va_window_size, ad.va_window_orig);
printf(" display start address (%d, %d), scan line width:%d\n",
ad.va_disp_start.x, ad.va_disp_start.y, ad.va_line_width);
printf(" reserved:0x%x\n", ad.va_unused0);
}
/*
* Write a value to a register and check that the write completed. These
* writes normally complete in a cycle or two, so one read should suffice.
* The very first read exists to flush the posted write to the device.
*/
static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
{
t1_write_reg_4(adapter, addr, val);
val = t1_read_reg_4(adapter, addr); /* flush */
if (!(t1_read_reg_4(adapter, addr) & F_BUSY))
return 0;
CH_ERR("%s: write to MC3 register 0x%x timed out\n",
adapter_name(adapter), addr);
return -EIO;
}
int t1_mc4_intr_handler(struct pemc4 *mc4)
{
adapter_t *adapter = mc4->adapter;
u32 cause = t1_read_reg_4(adapter, A_MC4_INT_CAUSE);
if (cause & F_MC4_CORR_ERR) {
mc4->intr_cnt.corr_err++;
CH_WARN("%s: MC4 correctable error at addr 0x%x, "
"data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
adapter_name(adapter),
G_MC4_CE_ADDR(t1_read_reg_4(adapter, A_MC4_CE_ADDR)),
t1_read_reg_4(adapter, A_MC4_CE_DATA0),
t1_read_reg_4(adapter, A_MC4_CE_DATA1),
t1_read_reg_4(adapter, A_MC4_CE_DATA2),
t1_read_reg_4(adapter, A_MC4_CE_DATA3),
t1_read_reg_4(adapter, A_MC4_CE_DATA4));
}
if (cause & F_MC4_UNCORR_ERR) {
mc4->intr_cnt.uncorr_err++;
CH_ALERT("%s: MC4 uncorrectable error at addr 0x%x, "
"data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
adapter_name(adapter),
G_MC4_UE_ADDR(t1_read_reg_4(adapter, A_MC4_UE_ADDR)),
t1_read_reg_4(adapter, A_MC4_UE_DATA0),
t1_read_reg_4(adapter, A_MC4_UE_DATA1),
t1_read_reg_4(adapter, A_MC4_UE_DATA2),
t1_read_reg_4(adapter, A_MC4_UE_DATA3),
t1_read_reg_4(adapter, A_MC4_UE_DATA4));
}
if (cause & F_MC4_ADDR_ERR) {
mc4->intr_cnt.addr_err++;
CH_ALERT("%s: MC4 address error\n", adapter_name(adapter));
}
if (cause & MC4_INT_FATAL)
t1_fatal_err(adapter);
t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, cause);
return 0;
}
/*
* Write a value to a register and check that the write completed. These
* writes normally complete in a cycle or two, so one read should suffice but
* just in case we give them a bit of grace period. Note that the very first
* read exists to flush the posted write to the device.
*/
static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
{
int attempts = 2;
t1_write_reg_4(adapter, addr, val);
val = t1_read_reg_4(adapter, addr); /* flush */
while (attempts--) {
if (!(t1_read_reg_4(adapter, addr) & F_BUSY))
return 0;
if (attempts)
DELAY_US(1);
}
CH_ERR("%s: write to MC4 register 0x%x timed out\n",
adapter_name(adapter), addr);
return -EIO;
}
STDMETHODIMP CArpScanner::GetAdapterInfo(LONG adapter, BSTR * name, BSTR* description, BSTR* ip, BSTR* mac, BOOL * ok)
{
if (this->pcap.LoadPCAP())
{
if (CheckAdapterNumber(adapter))
{
IN_ADDR raw_ip;
unsigned char raw_mac[6];
char mac_txt[18];
this->pcap.GetAdapterIP(adapter, &raw_ip, NULL);
this->pcap.GetAdapterMAC(adapter, raw_mac);
MAC2TXT(mac_txt, raw_mac);
CComBSTR adapter_ip(inet_ntoa(raw_ip));
CComBSTR adapter_mac(mac_txt);
CComBSTR adapter_descr(this->pcap.GetAdapterDescription(adapter));
CComBSTR adapter_name(this->pcap.GetAdapterName(adapter));
*name = adapter_name.Copy();
*description = adapter_descr.Copy();
*ip = adapter_ip.Copy();
*mac = adapter_mac.Copy();
*ok = true;
return S_OK;
}
else
{
*ok = false;
__raise this->OnScanError(E_INVALID_ADAPTER);
return S_FALSE;
}
}
else
{
*ok = false;
__raise this->OnScanError(E_WINPCAP_NOT_FOUND);
return S_FALSE;
}
}
void
fb_dump_adp_info(char *driver, video_adapter_t *adp, int level)
{
if (level <= 0)
return;
printf("%s%d: %s%d, %s, type:%s (%d), flags:0x%x\n",
FB_DRIVER_NAME, adp->va_index, driver, adp->va_unit, adp->va_name,
adapter_name(adp->va_type), adp->va_type, adp->va_flags);
printf("%s%d: port:0x%x-0x%x, crtc:0x%x, mem:0x%x 0x%x\n",
FB_DRIVER_NAME, adp->va_index,
adp->va_io_base, adp->va_io_base + adp->va_io_size - 1,
adp->va_crtc_addr, adp->va_mem_base, adp->va_mem_size);
printf("%s%d: init mode:%d, bios mode:%d, current mode:%d\n",
FB_DRIVER_NAME, adp->va_index,
adp->va_initial_mode, adp->va_initial_bios_mode, adp->va_mode);
printf("%s%d: window:%p size:%dk gran:%dk, buf:%p size:%dk\n",
FB_DRIVER_NAME, adp->va_index,
(void *)adp->va_window, (int)adp->va_window_size/1024,
(int)adp->va_window_gran/1024, (void *)adp->va_buffer,
(int)adp->va_buffer_size/1024);
}
// Creates an info struct if this is a valid frontend, otherwise returns NULL
struct devinfo * dvb_probe_frontend(unsigned adap, unsigned fe, int debug)
{
struct dvb_frontend_info feinfo;
char adapter[512];
char device[512];
struct devinfo *info = NULL ;
int fd;
if (debug)
{
fprintf(stderr, "dvb_probe_frontend(%u, %u)\n", adap, fe) ;
}
adapter_name(adap, adapter, sizeof(adapter));
frontend_name(fe, device, sizeof(device), adapter) ;
fd = open(device, O_RDONLY | O_NONBLOCK);
if (debug)
{
fprintf(stderr, " + adapter %s, device %s : fd %d (errno %d)\n", adapter, device, fd, errno) ;
if (fd < 0)
{
perror("Failed to open device") ;
}
}
if (-1 == fd)
return info ;
if (-1 == ioctl(fd, FE_GET_INFO, &feinfo)) {
if (debug)
perror("ioctl FE_GET_INFO");
close(fd);
return info ;
}
if (debug)
{
fprintf(stderr, " + got FE_GET_INFO\n", adap, fe) ;
}
info = (struct devinfo *)malloc(sizeof(struct devinfo));
memset(info,0,sizeof(struct devinfo));
strncpy(info->device, adapter, sizeof(info->device));
strncpy(info->name, feinfo.name, sizeof(info->name));
info->adapter_num = adap ;
info->frontend_num = fe ;
info->flags = (int)feinfo.caps ;
// extra
info->type = feinfo.type ;
info->frequency_min = feinfo.frequency_min ;
info->frequency_max = feinfo.frequency_max ;
info->frequency_stepsize = feinfo.frequency_stepsize ;
info->frequency_tolerance = feinfo.frequency_tolerance ;
info->symbol_rate_min = feinfo.symbol_rate_min ;
info->symbol_rate_max = feinfo.symbol_rate_max ;
info->symbol_rate_tolerance = feinfo.symbol_rate_tolerance ;
close(fd);
if (debug)
{
fprintf(stderr, " + end of probe\n") ;
}
return info;
}
int t1_mc4_init(struct pemc4 *mc4, unsigned int mc4_clock)
{
int attempts;
u32 val;
unsigned int width, ext_mode, slow_mode;
adapter_t *adapter = mc4->adapter;
/* Power up the FCRAMs. */
val = t1_read_reg_4(adapter, A_MC4_CFG);
t1_write_reg_4(adapter, A_MC4_CFG, val | F_POWER_UP);
val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */
if (is_MC4A(adapter)) {
slow_mode = val & F_MC4A_SLOW;
width = G_MC4A_WIDTH(val);
/* If we're not in slow mode, we are using the DLLs */
if (!slow_mode) {
/* Clear Reset */
val = t1_read_reg_4(adapter, A_MC4_STROBE);
t1_write_reg_4(adapter, A_MC4_STROBE,
val & ~F_SLAVE_DLL_RESET);
/* Wait for slave DLLs to lock */
DELAY_US(2 * 512 / (mc4_clock / 1000000) + 1);
}
} else {
slow_mode = val & F_MC4_SLOW;
width = !!(val & F_MC4_NARROW);
/* Initializes the master DLL and slave delay lines. */
if (t1_is_asic(adapter) && !slow_mode) {
val = t1_read_reg_4(adapter, A_MC4_STROBE);
t1_write_reg_4(adapter, A_MC4_STROBE,
val & ~F_MASTER_DLL_RESET);
/* Wait for the master DLL to lock. */
attempts = 100;
do {
DELAY_US(1);
val = t1_read_reg_4(adapter, A_MC4_STROBE);
} while (!(val & MC4_DLL_DONE) && --attempts);
if (!(val & MC4_DLL_DONE)) {
CH_ERR("%s: MC4 DLL lock failed\n",
adapter_name(adapter));
goto out_fail;
}
}
}
mc4->nwords = 4 >> width;
/* Set the FCRAM output drive strength and enable DLLs if needed */
ext_mode = t1_is_asic(adapter) && !slow_mode ? 0 : 1;
if (wrreg_wait(adapter, A_MC4_EXT_MODE, ext_mode))
goto out_fail;
/* Specify the FCRAM operating parameters */
if (wrreg_wait(adapter, A_MC4_MODE, 0x32))
goto out_fail;
/* Initiate an immediate refresh and wait for the write to complete. */
val = t1_read_reg_4(adapter, A_MC4_REFRESH);
if (wrreg_wait(adapter, A_MC4_REFRESH, val & ~F_REFRESH_ENABLE))
goto out_fail;
/* 2nd immediate refresh as before */
if (wrreg_wait(adapter, A_MC4_REFRESH, val & ~F_REFRESH_ENABLE))
goto out_fail;
/* Convert to KHz first to avoid 64-bit division. */
mc4_clock /= 1000; /* Hz->KHz */
mc4_clock = mc4_clock * 7812 + mc4_clock / 2; /* ns */
mc4_clock /= 1000000; /* KHz->MHz, ns->us */
/* Enable periodic refresh. */
t1_write_reg_4(adapter, A_MC4_REFRESH,
F_REFRESH_ENABLE | V_REFRESH_DIVISOR(mc4_clock));
(void) t1_read_reg_4(adapter, A_MC4_REFRESH); /* flush */
t1_write_reg_4(adapter, A_MC4_ECC_CNTL,
F_ECC_GENERATION_ENABLE | F_ECC_CHECK_ENABLE);
/* Use the BIST engine to clear all of the MC4 memory. */
t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0);
t1_write_reg_4(adapter, A_MC4_BIST_ADDR_END, (mc4->size << width) - 1);
t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0);
t1_write_reg_4(adapter, A_MC4_BIST_OP, V_OP(1) | 0x1f0);
(void) t1_read_reg_4(adapter, A_MC4_BIST_OP); /* flush */
attempts = 100;
do {
DELAY_MS(100);
val = t1_read_reg_4(adapter, A_MC4_BIST_OP);
} while ((val & F_BUSY) && --attempts);
if (val & F_BUSY) {
CH_ERR("%s: MC4 BIST timed out\n", adapter_name(adapter));
goto out_fail;
}
/* Enable normal memory accesses. */
val = t1_read_reg_4(adapter, A_MC4_CFG);
t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY);
val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */
return 0;
out_fail:
return -1;
}
int t1_mc3_init(struct pemc3 *mc3, unsigned int mc3_clock)
{
u32 val;
unsigned int width, fast_asic, attempts;
adapter_t *adapter = mc3->adapter;
/* Check to see if ASIC is running in slow mode. */
val = t1_read_reg_4(adapter, A_MC3_CFG);
width = is_MC3A(adapter) ? G_MC3_WIDTH(val) : 0;
fast_asic = t1_is_asic(adapter) && !(val & F_MC3_SLOW);
val &= ~(V_MC3_BANK_CYCLE(M_MC3_BANK_CYCLE) |
V_REFRESH_CYCLE(M_REFRESH_CYCLE) |
V_PRECHARGE_CYCLE(M_PRECHARGE_CYCLE) |
F_ACTIVE_TO_READ_WRITE_DELAY |
V_ACTIVE_TO_PRECHARGE_DELAY(M_ACTIVE_TO_PRECHARGE_DELAY) |
V_WRITE_RECOVERY_DELAY(M_WRITE_RECOVERY_DELAY));
if (mc3_clock <= 100000000)
val |= V_MC3_BANK_CYCLE(7) | V_REFRESH_CYCLE(4) |
V_PRECHARGE_CYCLE(2) | V_ACTIVE_TO_PRECHARGE_DELAY(5) |
V_WRITE_RECOVERY_DELAY(2);
else if (mc3_clock <= 133000000)
val |= V_MC3_BANK_CYCLE(9) | V_REFRESH_CYCLE(5) |
V_PRECHARGE_CYCLE(3) | F_ACTIVE_TO_READ_WRITE_DELAY |
V_ACTIVE_TO_PRECHARGE_DELAY(6) |
V_WRITE_RECOVERY_DELAY(2);
else
val |= V_MC3_BANK_CYCLE(0xA) | V_REFRESH_CYCLE(6) |
V_PRECHARGE_CYCLE(3) | F_ACTIVE_TO_READ_WRITE_DELAY |
V_ACTIVE_TO_PRECHARGE_DELAY(7) |
V_WRITE_RECOVERY_DELAY(3);
t1_write_reg_4(adapter, A_MC3_CFG, val);
val = t1_read_reg_4(adapter, A_MC3_CFG);
t1_write_reg_4(adapter, A_MC3_CFG, val | F_CLK_ENABLE);
val = t1_read_reg_4(adapter, A_MC3_CFG); /* flush */
if (fast_asic) { /* setup DLLs */
val = t1_read_reg_4(adapter, A_MC3_STROBE);
if (is_MC3A(adapter)) {
t1_write_reg_4(adapter, A_MC3_STROBE,
val & ~F_SLAVE_DLL_RESET);
/* Wait for slave DLLs to lock */
DELAY_US(2 * 512 / (mc3_clock / 1000000) + 1);
} else {
/* Initialize the master DLL and slave delay lines. */
t1_write_reg_4(adapter, A_MC3_STROBE,
val & ~F_MASTER_DLL_RESET);
/* Wait for the master DLL to lock. */
attempts = 100;
do {
DELAY_US(1);
val = t1_read_reg_4(adapter, A_MC3_STROBE);
} while (!(val & MC3_DLL_DONE) && --attempts);
if (!(val & MC3_DLL_DONE)) {
CH_ERR("%s: MC3 DLL lock failed\n",
adapter_name(adapter));
goto out_fail;
}
}
}
/* Initiate a precharge and wait for the precharge to complete. */
if (wrreg_wait(adapter, A_MC3_PRECHARG, 0))
goto out_fail;
/* Set the SDRAM output drive strength and enable DLLs if needed */
if (wrreg_wait(adapter, A_MC3_EXT_MODE, fast_asic ? 0 : 1))
goto out_fail;
/* Specify the SDRAM operating parameters. */
if (wrreg_wait(adapter, A_MC3_MODE, fast_asic ? 0x161 : 0x21))
goto out_fail;
/* Initiate a precharge and wait for the precharge to complete. */
if (wrreg_wait(adapter, A_MC3_PRECHARG, 0))
goto out_fail;
/* Initiate an immediate refresh and wait for the write to complete. */
val = t1_read_reg_4(adapter, A_MC3_REFRESH);
if (wrreg_wait(adapter, A_MC3_REFRESH, val & ~F_REFRESH_ENABLE))
goto out_fail;
/* 2nd immediate refresh as before */
if (wrreg_wait(adapter, A_MC3_REFRESH, val & ~F_REFRESH_ENABLE))
goto out_fail;
/* Specify the SDRAM operating parameters. */
if (wrreg_wait(adapter, A_MC3_MODE, fast_asic ? 0x61 : 0x21))
goto out_fail;
/* Convert to KHz first to avoid 64-bit division. */
mc3_clock /= 1000; /* Hz->KHz */
mc3_clock = mc3_clock * 7812 + mc3_clock / 2; /* ns */
mc3_clock /= 1000000; /* KHz->MHz, ns->us */
/* Enable periodic refresh. */
t1_write_reg_4(adapter, A_MC3_REFRESH,
F_REFRESH_ENABLE | V_REFRESH_DIVISOR(mc3_clock));
(void) t1_read_reg_4(adapter, A_MC3_REFRESH); /* flush */
t1_write_reg_4(adapter, A_MC3_ECC_CNTL,
F_ECC_GENERATION_ENABLE | F_ECC_CHECK_ENABLE);
/* Use the BIST engine to clear MC3 memory and initialize ECC. */
t1_write_reg_4(adapter, A_MC3_BIST_ADDR_BEG, 0);
t1_write_reg_4(adapter, A_MC3_BIST_ADDR_END, (mc3->size << width) - 1);
t1_write_reg_4(adapter, A_MC3_BIST_DATA, 0);
t1_write_reg_4(adapter, A_MC3_BIST_OP, V_OP(1) | 0x1f0);
(void) t1_read_reg_4(adapter, A_MC3_BIST_OP); /* flush */
attempts = 100;
do {
DELAY_MS(100);
val = t1_read_reg_4(adapter, A_MC3_BIST_OP);
} while ((val & F_BUSY) && --attempts);
if (val & F_BUSY) {
CH_ERR("%s: MC3 BIST timed out\n", adapter_name(adapter));
goto out_fail;
}
/* Enable normal memory accesses. */
val = t1_read_reg_4(adapter, A_MC3_CFG);
t1_write_reg_4(adapter, A_MC3_CFG, val | F_READY);
return 0;
out_fail:
return -1;
}
int t1_mc3_intr_handler(struct pemc3 *mc3)
{
adapter_t *adapter = mc3->adapter;
int cause_reg = A_MC3_INT_CAUSE;
u32 cause;
#ifdef CONFIG_CHELSIO_T1_1G
if (!t1_is_asic(adapter))
cause_reg = FPGA_MC3_REG_INTRCAUSE;
#endif
cause = t1_read_reg_4(adapter, cause_reg);
if (cause & F_MC3_CORR_ERR) {
mc3->intr_cnt.corr_err++;
CH_WARN("%s: MC3 correctable error at addr 0x%x, "
"data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
adapter_name(adapter),
G_MC3_CE_ADDR(t1_read_reg_4(adapter, A_MC3_CE_ADDR)),
t1_read_reg_4(adapter, A_MC3_CE_DATA0),
t1_read_reg_4(adapter, A_MC3_CE_DATA1),
t1_read_reg_4(adapter, A_MC3_CE_DATA2),
t1_read_reg_4(adapter, A_MC3_CE_DATA3),
t1_read_reg_4(adapter, A_MC3_CE_DATA4));
}
if (cause & F_MC3_UNCORR_ERR) {
mc3->intr_cnt.uncorr_err++;
CH_ALERT("%s: MC3 uncorrectable error at addr 0x%x, "
"data 0x%x 0x%x 0x%x 0x%x 0x%x\n",
adapter_name(adapter),
G_MC3_UE_ADDR(t1_read_reg_4(adapter, A_MC3_UE_ADDR)),
t1_read_reg_4(adapter, A_MC3_UE_DATA0),
t1_read_reg_4(adapter, A_MC3_UE_DATA1),
t1_read_reg_4(adapter, A_MC3_UE_DATA2),
t1_read_reg_4(adapter, A_MC3_UE_DATA3),
t1_read_reg_4(adapter, A_MC3_UE_DATA4));
}
if (G_MC3_PARITY_ERR(cause)) {
mc3->intr_cnt.parity_err++;
CH_ALERT("%s: MC3 parity error 0x%x\n", adapter_name(adapter),
G_MC3_PARITY_ERR(cause));
}
if (cause & F_MC3_ADDR_ERR) {
mc3->intr_cnt.addr_err++;
CH_ALERT("%s: MC3 address error\n", adapter_name(adapter));
}
if (cause & MC3_INTR_FATAL)
t1_fatal_err(adapter);
if (t1_is_T1B(adapter)) {
/*
* Workaround for T1B bug: we must write to enable register to
* clear interrupts.
*/
t1_write_reg_4(adapter, A_MC3_INT_ENABLE, cause);
/* restore enable */
t1_write_reg_4(adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK);
} else
t1_write_reg_4(adapter, cause_reg, cause);
return 0;
}
