/* setup code for a handoff from a version 2 PMON 2000 PROM */
void PMON_v2_setup(void)
{
/* Some wired TLB entries for the MV64340 and perhiperals. The
MV64340 is going to be hit on every IRQ anyway - there's
absolutely no point in letting it be a random TLB entry, as
it'll just cause needless churning of the TLB. And we use
the other half for the serial port, which is just a PITA
otherwise :)
Device Physical Virtual
MV64340 Internal Regs 0xf4000000 0xf4000000
Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
NVRAM (CS1) 0xfc800000 0xfc800000
UARTs (CS2) 0xfd000000 0xfd000000
Internal SRAM 0xfe000000 0xfe000000
M-Systems DOC (CS3) 0xff000000 0xff000000
*/
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
/* m-sys and internal SRAM */
add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
mv64340_base = 0xf4000000;
}
/*
* setup code for a handoff from a version 2 PMON 2000 PROM
*/
void setup_wired_tlb_entries(void)
{
write_c0_wired(0);
local_flush_tlb_all();
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
}
static __init void wire_stupidity_into_tlb(void)
{
#ifdef CONFIG_32BIT
write_c0_wired(0);
local_flush_tlb_all();
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
0xf4000000UL, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
0xfc000000UL, PM_16M);
// /* m-sys and internal SRAM */
// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
// 0xfe000000UL, PM_16M);
marvell_base = 0xf4000000;
//mv64340_sram_base = 0xfe000000; /* Currently unused */
#endif
}
/*
* On systems with i8259-style interrupt controllers we assume for
* driver compatibility reasons interrupts 0 - 15 to be the i8259
* interrupts even if the hardware uses a different interrupt numbering.
*/
void __init arch_init_irq(void)
{
/*
* this is a hack to get back the still needed wired mapping
* killed by init_mm()
*/
/* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
/* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
/* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
init_i8259_irqs(); /* Integrated i8259 */
mips_cpu_irq_init();
init_r4030_ints();
change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
}
void prom_putchar(char c)
{
extern void add_wired_entry(unsigned long entrylo0,
unsigned long entrylo1,
unsigned long entryhi,
unsigned long pagemask);
u32 tx_level;
if ((added_wired_in_prom_putchar == 0) ||
(tlb_is_inited && added_wired_in_prom_putchar == 1)) {
add_wired_entry((0xd << 22) | (2 << 3) | 7,
(0xe << 22) | (2 << 3) | 7,
0xd0000000,
PM_64M);
if (added_wired_in_prom_putchar++ == 0) {
u32 *reg, val;
/* uart 1 pin mux and pad control */
reg = (u32 *)(0xd0000000 | BCHP_CM_TOP_CTRL_PIN_MUX_PAD_CTRL_3);
val = *reg;
val &= ~(BCHP_CM_TOP_CTRL_PIN_MUX_PAD_CTRL_3_bnm_gpio_041_pad_ctrl_MASK |
BCHP_CM_TOP_CTRL_PIN_MUX_PAD_CTRL_3_bnm_gpio_042_pad_ctrl_MASK);
*reg = val;
reg = (u32 *)(0xd0000000 | BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5);
val = *reg;
val &= ~(BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5_bnm_gpio_041_MASK |
BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5_bnm_gpio_042_MASK);
val |= (BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5_bnm_gpio_041_BNM_UART_RXD_1 <<
BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5_bnm_gpio_041_SHIFT);
val |= (BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5_bnm_gpio_042_BNM_UART_TXD_1 <<
BCHP_CM_TOP_CTRL_PIN_MUX_CTRL_5_bnm_gpio_042_SHIFT);
*reg = val;
reg = (u32 *)(0xd0000000 | BCHP_UART1_PER_CONTROL);
*reg = 0x00e03710;
reg = (u32 *)(0xd0000000 | BCHP_UART1_PER_BAUDWORD);
*reg = 0xe;
}
}
while(1)
{
tx_level = *(u32 *)(0xd0000000 | BCHP_UART1_PER_MISC_CTL);
tx_level = tx_level >> 24;
tx_level &= 0x1f;
if(tx_level < 14)
break;
}
*(u32 *)(0xd0000000 | BCHP_UART1_PER_UARTFIFO) = (unsigned int)c;
}
