void model_fxx_update_microcode(unsigned cpu_deviceid) { unsigned equivalent_processor_rev_id; /* Update the microcode */ equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); if(equivalent_processor_rev_id != 0) amd_update_microcode(microcode_updates, equivalent_processor_rev_id); }
void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) { const void *ucode; size_t ucode_len; uint32_t i; for (i = 0; i < ARRAY_SIZE(microcode_cbfs_file); i++) { if (equivalent_processor_rev_id == 0) { UCODE_DEBUG("rev id not found. Skipping microcode patch!\n"); return; } #ifdef __PRE_RAM__ #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) spin_lock(romstage_microcode_cbfs_lock()); #endif #endif ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { UCODE_DEBUG("microcode file not found. Skipping updates.\n"); #ifdef __PRE_RAM__ #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) spin_unlock(romstage_microcode_cbfs_lock()); #endif #endif return; } amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); #ifdef __PRE_RAM__ #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) spin_unlock(romstage_microcode_cbfs_lock()); #endif #endif } }