void clk_switch(int flag)
{
int i;
if (flag) {
for (i = CLK_COUNT - 1; i >= 0; i--) {
if (clk_flag[i]) {
if ((clks[i] == P_HHI_VID_CLK_CNTL)||(clks[i] == P_HHI_VIID_CLK_CNTL)) {
aml_set_reg32_bits(clks[i],clk_flag[i],19,2);
} else if (clks[i] == P_HHI_MPEG_CLK_CNTL) {
if (uart_rate_backup == 0) {
struct clk* sys_clk = clk_get_sys("clk81", NULL);
sys_clk->rate = 0;
uart_rate_backup = clk_get_rate(sys_clk);
}
wait_uart_empty();
aml_set_reg32_mask(clks[i],(1<<7));//gate on pll
udelay(10);
aml_set_reg32_mask(clks[i],(1<<8));//switch to pll
udelay(10);
aml_clr_reg32_mask(P_UART0_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART0_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART0_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_UART1_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART1_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART1_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART2_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART2_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART2_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART_REG5, 1, 23, 1);
} else {
aml_set_reg32_mask(clks[i],(1<<8));
}
clk_flag[i] = 0;
printk(KERN_INFO "clk %s(%x) on\n", clks_name[i], clks[i]);
}
#ifdef M6_TV_CLK_DEBUG
if (clk_aud_23)
aml_set_reg32_mask(P_HHI_AUD_CLK_CNTL,(1<<23));
if (clk_vdec_24)
aml_set_reg32_mask(P_HHI_VDEC_CLK_CNTL,(1<<24));
#endif
}
} else {
for (i = 0; i < CLK_COUNT; i++) {
if ((clks[i] == P_HHI_VID_CLK_CNTL)||(clks[i] == P_HHI_VIID_CLK_CNTL)) {
clk_flag[i] = aml_get_reg32_bits(clks[i], 19, 2);
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1<<19)|(1<<20));
}
} else if (clks[i] == P_HHI_MPEG_CLK_CNTL) {
if (aml_read_reg32(clks[i]) & (1 << 8)) {
if (xtal_uart_rate_backup == 0) {//if no early suspend supported
struct clk* sys_clk = clk_get_sys("xtal", NULL);
xtal_uart_rate_backup = clk_get_rate(sys_clk);
}
wait_uart_empty();
clk_flag[i] = 1;
aml_clr_reg32_mask(clks[i], (1 << 8)); // 24M
udelay(10);
aml_clr_reg32_mask(clks[i], (1 << 7)); // 24M
udelay(10);
aml_clr_reg32_mask(P_UART0_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART0_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART0_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_UART1_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART1_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART1_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART2_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART2_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART2_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART_REG5, 1, 23, 1);
}
}
#ifdef M6_TV_CLK_DEBUG
else if (clks[i] == P_HHI_AUD_CLK_CNTL) {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
clk_aud_23 = aml_get_reg32_bits(clks[i], 23, 1) ? 1 : 0;
if (clk_aud_23) {
aml_clr_reg32_mask(clks[i], (1 << 23));
}
}
else if (clks[i] == P_HHI_VDEC_CLK_CNTL) {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
clk_vdec_24 = aml_get_reg32_bits(clks[i], 24, 1) ? 1 : 0;
if (clk_vdec_24) {
aml_clr_reg32_mask(clks[i], (1 << 24));
}
}
else {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
}
#else
else {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
}
#endif
if (clk_flag[i]) {
printk(KERN_INFO "clk %s(%x) off\n", clks_name[i], clks[i]);
wait_uart_empty();
}
}
}
static int _switch_gate(mod_type_t type, int flag)
{
int ret = 0;
switch(type) {
case MOD_VDEC:
PRINT_INFO("turn %s vdec module\n", flag?"on":"off");
if (flag) {
GATE_ON(DOS);
aml_set_reg32_mask(P_HHI_VDEC_CLK_CNTL, 1 << 8);
} else {
GATE_OFF(DOS);
aml_clr_reg32_mask(P_HHI_VDEC_CLK_CNTL, 1 << 8);
}
break;
case MOD_AUDIO:
PRINT_INFO("turn %s audio module\n", flag?"on":"off");
if (flag) {
GATE_ON(AIU_AMCLK_MEASURE);
GATE_ON(AIU_AIFIFO2);
GATE_ON(AIU_AUD_MIXER);
GATE_ON(AIU_MIXER_REG);
GATE_ON(AIU_IEC958);
GATE_ON(AIU_AI_TOP_GLUE);
GATE_ON(AUD_BUF);
GATE_ON(AIU_I2S_OUT);
GATE_ON(AIU_AMCLK); //this gate should not be turned off
GATE_ON(AIU_ICE958_AMCLK);
GATE_ON(AIU_AOCLK);
//GATE_ON(AUD_IN);
GATE_ON(AIU_ADC);
GATE_ON(AIU_AUDIN_SCLK);
} else {
GATE_OFF(AIU_AMCLK_MEASURE);
GATE_OFF(AIU_AIFIFO2);
GATE_OFF(AIU_AUD_MIXER);
GATE_OFF(AIU_MIXER_REG);
GATE_OFF(AIU_IEC958);
GATE_OFF(AIU_AI_TOP_GLUE);
GATE_OFF(AUD_BUF);
GATE_OFF(AIU_I2S_OUT);
GATE_OFF(AIU_AMCLK); //this gate should not be turned off
GATE_OFF(AIU_ICE958_AMCLK);
GATE_OFF(AIU_AOCLK);
//GATE_OFF(AUD_IN);
GATE_OFF(AIU_ADC);
GATE_OFF(AIU_AUDIN_SCLK);
}
break;
case MOD_HDMI:
PRINT_INFO("turn %s hdmi module\n", flag?"on":"off");
if (flag) {
GATE_ON(HDMI_INTR_SYNC);
GATE_ON(HDMI_PCLK);
GATE_ON(VCLK1_HDMI);
} else {
GATE_OFF(HDMI_INTR_SYNC);
GATE_OFF(HDMI_PCLK);
GATE_OFF(VCLK1_HDMI);
}
break;
case MOD_VENC:
PRINT_INFO("turn %s venc module\n", flag?"on":"off");
if (flag) {
GATE_ON(VCLK2_VENCI);
GATE_ON(VCLK2_VENCI1);
GATE_ON(VCLK2_VENCP);
GATE_ON(VCLK2_VENCP1);
GATE_ON(VENC_P_TOP);
GATE_ON(VENC_I_TOP);
GATE_ON(VENCI_INT);
GATE_ON(VENCP_INT);
GATE_ON(VCLK2_ENCI);
GATE_ON(VCLK2_ENCP);
GATE_ON(VCLK2_VENCT);
GATE_ON(VCLK2_VENCT1);
GATE_ON(VCLK2_OTHER);
GATE_ON(VCLK2_OTHER1);
GATE_ON(ENC480P);
GATE_ON(VENC_DAC);
GATE_ON(DAC_CLK);
} else {
GATE_OFF(VCLK2_VENCI);
GATE_OFF(VCLK2_VENCI1);
GATE_OFF(VCLK2_VENCP);
#if !defined(CONFIG_MESON_POWER_PROFILE_LOW)
GATE_OFF(VCLK2_VENCP1);
GATE_OFF(VENC_P_TOP);
GATE_OFF(VENC_I_TOP);
#endif
GATE_OFF(VENCI_INT);
#if !defined(CONFIG_MESON_POWER_PROFILE_LOW)
GATE_OFF(VENCP_INT);
#endif
GATE_OFF(VCLK2_ENCI);
#if !defined(CONFIG_MESON_POWER_PROFILE_LOW)
GATE_OFF(VCLK2_ENCP);
#endif
GATE_OFF(VCLK2_VENCT);
GATE_OFF(VCLK2_VENCT1);
GATE_OFF(VCLK2_OTHER);
GATE_OFF(VCLK2_OTHER1);
GATE_OFF(ENC480P);
#if !defined(CONFIG_MESON_POWER_PROFILE_LOW)
GATE_OFF(VENC_DAC);
#endif
GATE_OFF(DAC_CLK);
}
break;
case MOD_TCON:
PRINT_INFO("turn %s tcon module\n", flag?"on":"off");
if (flag) {
GATE_ON(VENC_T_TOP);
GATE_ON(VENCT_INT);
GATE_ON(VCLK2_ENCT);
} else {
GATE_OFF(VENC_T_TOP);
GATE_OFF(VENCT_INT);
GATE_OFF(VCLK2_ENCT);
}
break;
case MOD_LVDS:
PRINT_INFO("turn %s lvds module\n", flag?"on":"off");
if (flag) {
GATE_ON(VENC_L_TOP);
GATE_ON(VENCL_INT);
GATE_ON(VCLK2_ENCL);
} else {
GATE_OFF(VENC_L_TOP);
GATE_OFF(VENCL_INT);
GATE_OFF(VCLK2_ENCL);
}
break;
case MOD_MIPI:
PRINT_INFO("turn %s mipi module\n", flag?"on":"off");
if (flag) {
GATE_ON(MIPI_APB_CLK);
GATE_ON(MIPI_SYS_CLK);
GATE_ON(MIPI_PHY);
} else {
GATE_OFF(MIPI_APB_CLK);
GATE_OFF(MIPI_SYS_CLK);
GATE_OFF(MIPI_PHY);
}
break;
case MOD_BT656:
PRINT_INFO("turn %s bt656 module\n", flag?"on":"off");
if (flag) {
GATE_ON(BT656_IN);
} else {
GATE_OFF(BT656_IN);
}
break;
case MOD_SPI:
PRINT_INFO("turn %s spi module\n", flag?"on":"off");
if (flag) {
GATE_ON(SPICC);
GATE_ON(SPI1);
GATE_ON(SPI2);
} else {
GATE_OFF(SPICC);
GATE_OFF(SPI1);
GATE_OFF(SPI2);
}
break;
case MOD_UART0:
PRINT_INFO("turn %s uart0 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART0);
} else {
GATE_OFF(UART0);
}
break;
case MOD_UART1:
PRINT_INFO("turn %s uart1 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART1);
} else {
GATE_OFF(UART1);
}
break;
case MOD_UART2:
PRINT_INFO("turn %s uart2 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART2);
} else {
GATE_OFF(UART2);
}
break;
case MOD_UART3:
PRINT_INFO("turn %s uart3 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART3);
} else {
GATE_OFF(UART3);
}
break;
case MOD_ROM:
PRINT_INFO("turn %s rom module\n", flag?"on":"off");
if (flag) {
GATE_ON(ROM_CLK);
} else {
GATE_OFF(ROM_CLK);
}
break;
case MOD_EFUSE:
PRINT_INFO("turn %s efuse module\n", flag?"on":"off");
if (flag) {
GATE_ON(EFUSE);
} else {
GATE_OFF(EFUSE);
}
break;
case MOD_RANDOM_NUM_GEN:
PRINT_INFO("turn %s random_num_gen module\n", flag?"on":"off");
if (flag) {
GATE_ON(RANDOM_NUM_GEN);
} else {
GATE_OFF(RANDOM_NUM_GEN);
}
break;
case MOD_ETHERNET:
PRINT_INFO("turn %s ethernet module\n", flag?"on":"off");
if (flag) {
GATE_ON(ETHERNET);
} else {
GATE_OFF(ETHERNET);
}
break;
case MOD_MEDIA_CPU:
PRINT_INFO("trun %s Audio DSP\n", flag? " on" : "off");
if(flag){
GATE_ON(MEDIA_CPU);
}else{
GATE_OFF(MEDIA_CPU);
}
break;
case MOD_GE2D:
PRINT_INFO("trun %s GE2D\n", flag? " on" : "off");
if(flag){
GATE_ON(GE2D);
}else{
GATE_OFF(GE2D);
}
break;
case MOD_VIDEO_IN:
PRINT_INFO("trun %s video_in\n", flag? " on" : "off");
if(flag){
GATE_ON(VIDEO_IN);
}else{
GATE_OFF(VIDEO_IN);
}
break;
case MOD_VIU2:
PRINT_INFO("trun %s viu2\n", flag? " on" : "off");
if(flag){
GATE_ON(VIU2);
}else{
GATE_OFF(VIU2);
}
break;
case MOD_AUD_IN:
PRINT_INFO("trun %s audio_in\n", flag? " on" : "off");
#if 0
if(flag){
GATE_ON(AIU_ADC);
GATE_ON(AIU_AUDIN_SCLK);
}else{
GATE_OFF(AIU_ADC);
GATE_OFF(AIU_AUDIN_SCLK);
}
#endif
break;
case MOD_AUD_OUT:
PRINT_INFO("trun %s audio_out\n", flag? " on" : "off");
if(flag){
}else{
}
break;
case MOD_AHB:
PRINT_INFO("trun %s ahb\n", flag? " on" : "off");
if(flag){
GATE_ON(AHB_ARB0);
GATE_ON(AHB_BRIDGE);
GATE_ON(AHB_DATA_BUS);
GATE_ON(AHB_CONTROL_BUS);
}else{
GATE_OFF(AHB_ARB0);
GATE_OFF(AHB_BRIDGE);
GATE_OFF(AHB_DATA_BUS);
GATE_OFF(AHB_CONTROL_BUS);
}
break;
case MOD_DEMUX:
PRINT_INFO("trun %s demux\n", flag? " on" : "off");
if(flag){
GATE_ON(DEMUX);
}else{
GATE_OFF(DEMUX);
}
break;
case MOD_SMART_CARD:
PRINT_INFO("trun %s smart card\n", flag? " on" : "off");
if(flag){
GATE_ON(SMART_CARD_MPEG_DOMAIN);
}else{
GATE_OFF(SMART_CARD_MPEG_DOMAIN);
}
break;
case MOD_SDHC:
PRINT_INFO("trun %s sdhc\n", flag? " on" : "off");
if(flag){
GATE_ON(SDHC);
}else{
GATE_OFF(SDHC);
}
break;
case MOD_STREAM:
PRINT_INFO("trun %s stream\n", flag? " on" : "off");
if(flag){
GATE_ON(STREAM);
}else{
GATE_OFF(STREAM);
}
break;
case MOD_BLK_MOV:
PRINT_INFO("trun %s blk_mov\n", flag? " on" : "off");
if(flag){
GATE_ON(BLK_MOV);
}else{
GATE_OFF(BLK_MOV);
}
break;
case MOD_MISC_DVIN:
PRINT_INFO("trun %s dvin\n", flag? " on" : "off");
if(flag){
GATE_ON(MISC_DVIN);
}else{
GATE_OFF(MISC_DVIN);
}
break;
case MOD_MISC_RDMA:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(MISC_RDMA);
}else{
GATE_OFF(MISC_RDMA);
}
break;
case MOD_USB0:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(USB0);
GATE_ON(MISC_USB0_TO_DDR);
}else{
GATE_OFF(USB0);
GATE_ON(MISC_USB0_TO_DDR);
}
break;
case MOD_USB1:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(USB1);
GATE_ON(MISC_USB1_TO_DDR);
}else{
GATE_OFF(USB1);
GATE_ON(MISC_USB1_TO_DDR);
}
break;
case MOD_SDIO:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(SDIO);
}else{
GATE_OFF(SDIO);
}
break;
case MOD_VI_CORE:
PRINT_INFO("trun %s vi core\n", flag? " on" : "off");
if(flag){
GATE_ON(VI_CORE);
}else{
GATE_OFF(VI_CORE);
}
break;
case MOD_LED_PWM:
PRINT_INFO("trun %s led pwm\n", flag? " on" : "off");
if(flag){
GATE_ON(LED_PWM);
}else{
GATE_OFF(LED_PWM);
}
break;
case MOD_VDAC:
printk("trun %s vdac\n", flag? " on" : "off");
if(flag){
#ifdef CONFIG_ARCH_MESON6
if( ((aml_read_reg32(P_VPU_VIU_VENC_MUX_CTRL)&0xf)==0x5) && (aml_read_reg32(P_ENCI_DACSEL_0)==0x1111) )
aml_write_reg32(P_VENC_VDAC_SETTING, 0x5);// 480cvbs/576cvbs mode
else
aml_write_reg32(P_VENC_VDAC_SETTING, 0x0);
#else
aml_write_reg32(P_VENC_VDAC_SETTING, 0x0);
#endif
}else{
aml_write_reg32(P_VENC_VDAC_SETTING, 0xffffffff);
}
break;
default:
PRINT_INFO("mod type not support\n");
ret = -1;
break;
}
return ret;
}
void disable_watchdog(void)
{
printk(KERN_INFO "** disable watchdog\n");
aml_write_reg32(P_WATCHDOG_RESET, 0);
aml_clr_reg32_mask(P_WATCHDOG_TC,(1 << WATCHDOG_ENABLE_BIT));
}
static void uart_change_buad(unsigned reg,unsigned clk_rate){
aml_clr_reg32_mask(reg, 0x7FFFFF);
aml_set_reg32_bits(reg, (((clk_rate / (115200 * 4)) - 1) & 0x7fffff)|(1<<23), 0, 24);
}
