static void __init MP_processor_info(struct mpc_config_processor *m)
{
int ver, logical_apicid;
physid_mask_t apic_cpus;
if (!(m->mpc_cpuflag & CPU_ENABLED))
return;
logical_apicid = m->mpc_apicid;
printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
m->mpc_apicid,
(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
m->mpc_apicver);
if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
boot_cpu_physical_apicid = m->mpc_apicid;
ver = m->mpc_apicver;
if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
m->mpc_apicid, MAX_APICS);
return;
}
apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
/*
* Validate version
*/
if (ver == 0x0) {
printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
"fixing up to 0x10. (tell your hw vendor)\n",
m->mpc_apicid);
ver = 0x10;
}
apic_version[m->mpc_apicid] = ver;
}
static void __devinit MP_processor_info (struct mpc_config_processor *m)
{
int ver, apicid;
physid_mask_t phys_cpu;
if (!(m->mpc_cpuflag & CPU_ENABLED))
return;
apicid = mpc_apic_id(m, translation_table[mpc_record]);
if (m->mpc_featureflag&(1<<0))
Dprintk(" Floating point unit present.\n");
if (m->mpc_featureflag&(1<<7))
Dprintk(" Machine Exception supported.\n");
if (m->mpc_featureflag&(1<<8))
Dprintk(" 64 bit compare & exchange supported.\n");
if (m->mpc_featureflag&(1<<9))
Dprintk(" Internal APIC present.\n");
if (m->mpc_featureflag&(1<<11))
Dprintk(" SEP present.\n");
if (m->mpc_featureflag&(1<<12))
Dprintk(" MTRR present.\n");
if (m->mpc_featureflag&(1<<13))
Dprintk(" PGE present.\n");
if (m->mpc_featureflag&(1<<14))
Dprintk(" MCA present.\n");
if (m->mpc_featureflag&(1<<15))
Dprintk(" CMOV present.\n");
if (m->mpc_featureflag&(1<<16))
Dprintk(" PAT present.\n");
if (m->mpc_featureflag&(1<<17))
Dprintk(" PSE present.\n");
if (m->mpc_featureflag&(1<<18))
Dprintk(" PSN present.\n");
if (m->mpc_featureflag&(1<<19))
Dprintk(" Cache Line Flush Instruction present.\n");
/* 20 Reserved */
if (m->mpc_featureflag&(1<<21))
Dprintk(" Debug Trace and EMON Store present.\n");
if (m->mpc_featureflag&(1<<22))
Dprintk(" ACPI Thermal Throttle Registers present.\n");
if (m->mpc_featureflag&(1<<23))
Dprintk(" MMX present.\n");
if (m->mpc_featureflag&(1<<24))
Dprintk(" FXSR present.\n");
if (m->mpc_featureflag&(1<<25))
Dprintk(" XMM present.\n");
if (m->mpc_featureflag&(1<<26))
Dprintk(" Willamette New Instructions present.\n");
if (m->mpc_featureflag&(1<<27))
Dprintk(" Self Snoop present.\n");
if (m->mpc_featureflag&(1<<28))
Dprintk(" HT present.\n");
if (m->mpc_featureflag&(1<<29))
Dprintk(" Thermal Monitor present.\n");
/* 30, 31 Reserved */
if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
Dprintk(" Bootup CPU\n");
boot_cpu_physical_apicid = m->mpc_apicid;
}
ver = m->mpc_apicver;
/*
* Validate version
*/
if (ver == 0x0) {
printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
"fixing up to 0x10. (tell your hw vendor)\n",
m->mpc_apicid);
ver = 0x10;
}
apic_version[m->mpc_apicid] = ver;
phys_cpu = apicid_to_cpu_present(apicid);
physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
if (num_processors >= NR_CPUS) {
printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
" Processor ignored.\n", NR_CPUS);
return;
}
if (num_processors >= maxcpus) {
printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
" Processor ignored.\n", maxcpus);
return;
}
cpu_set(num_processors, cpu_possible_map);
num_processors++;
/*
* Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
* but we need to work other dependencies like SMP_SUSPEND etc
* before this can be done without some confusion.
* if (CPU_HOTPLUG_ENABLED || num_processors > 8)
* - Ashok Raj <*****@*****.**>
*/
if (num_processors > 8) {
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
if (!APIC_XAPIC(ver)) {
def_to_bigsmp = 0;
break;
}
/* If P4 and above fall through */
case X86_VENDOR_AMD:
def_to_bigsmp = 1;
}
}
bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
}
/* Return xen's logical cpu_id of the new added cpu or <0 if error */
static int __devinit MP_processor_info_x(struct mpc_config_processor *m,
u32 apicidx)
{
int ver, apicid, cpu = 0;
physid_mask_t phys_cpu;
if (!(m->mpc_cpuflag & CPU_ENABLED))
return -EINVAL;
apicid = mpc_apic_id(m, apicidx, translation_table[mpc_record]);
if (m->mpc_featureflag&(1<<0))
Dprintk(" Floating point unit present.\n");
if (m->mpc_featureflag&(1<<7))
Dprintk(" Machine Exception supported.\n");
if (m->mpc_featureflag&(1<<8))
Dprintk(" 64 bit compare & exchange supported.\n");
if (m->mpc_featureflag&(1<<9))
Dprintk(" Internal APIC present.\n");
if (m->mpc_featureflag&(1<<11))
Dprintk(" SEP present.\n");
if (m->mpc_featureflag&(1<<12))
Dprintk(" MTRR present.\n");
if (m->mpc_featureflag&(1<<13))
Dprintk(" PGE present.\n");
if (m->mpc_featureflag&(1<<14))
Dprintk(" MCA present.\n");
if (m->mpc_featureflag&(1<<15))
Dprintk(" CMOV present.\n");
if (m->mpc_featureflag&(1<<16))
Dprintk(" PAT present.\n");
if (m->mpc_featureflag&(1<<17))
Dprintk(" PSE present.\n");
if (m->mpc_featureflag&(1<<18))
Dprintk(" PSN present.\n");
if (m->mpc_featureflag&(1<<19))
Dprintk(" Cache Line Flush Instruction present.\n");
/* 20 Reserved */
if (m->mpc_featureflag&(1<<21))
Dprintk(" Debug Trace and EMON Store present.\n");
if (m->mpc_featureflag&(1<<22))
Dprintk(" ACPI Thermal Throttle Registers present.\n");
if (m->mpc_featureflag&(1<<23))
Dprintk(" MMX present.\n");
if (m->mpc_featureflag&(1<<24))
Dprintk(" FXSR present.\n");
if (m->mpc_featureflag&(1<<25))
Dprintk(" XMM present.\n");
if (m->mpc_featureflag&(1<<26))
Dprintk(" Willamette New Instructions present.\n");
if (m->mpc_featureflag&(1<<27))
Dprintk(" Self Snoop present.\n");
if (m->mpc_featureflag&(1<<28))
Dprintk(" HT present.\n");
if (m->mpc_featureflag&(1<<29))
Dprintk(" Thermal Monitor present.\n");
/* 30, 31 Reserved */
if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
Dprintk(" Bootup CPU\n");
boot_cpu_physical_apicid = apicid;
}
ver = m->mpc_apicver;
/*
* Validate version
*/
if (ver == 0x0) {
printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
"fixing up to 0x10. (tell your hw vendor)\n",
apicid);
ver = 0x10;
}
apic_version[apicid] = ver;
phys_cpu = apicid_to_cpu_present(apicid);
physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
if (num_processors >= NR_CPUS) {
printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
" Processor ignored.\n", NR_CPUS);
return -ENOSPC;
}
if (num_processors >= maxcpus) {
printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
" Processor ignored.\n", maxcpus);
return -ENOSPC;
}
/* Boot cpu has been marked present in smp_prepare_boot_cpu */
if (!(m->mpc_cpuflag & CPU_BOOTPROCESSOR)) {
cpu = alloc_cpu_id();
if (cpu < 0) {
printk(KERN_WARNING "WARNING: Can't alloc cpu_id."
" Processor with apicid %i ignored\n", apicid);
return cpu;
}
x86_cpu_to_apicid[cpu] = apicid;
cpu_set(cpu, cpu_present_map);
}
if (++num_processors > 8) {
/*
* No need for processor or APIC checks: physical delivery
* (bigsmp) mode should always work.
*/
def_to_bigsmp = 1;
}
return cpu;
}
