static int ar5523_host_available(struct ar5523 *ar)
{
struct ar5523_cmd_host_available setup;
/* inform target the host is available */
setup.sw_ver_major = cpu_to_be32(ATH_SW_VER_MAJOR);
setup.sw_ver_minor = cpu_to_be32(ATH_SW_VER_MINOR);
setup.sw_ver_patch = cpu_to_be32(ATH_SW_VER_PATCH);
setup.sw_ver_build = cpu_to_be32(ATH_SW_VER_BUILD);
return ar5523_cmd_read(ar, WDCMSG_HOST_AVAILABLE,
&setup, sizeof(setup), NULL, 0, 0);
}
static int ar5523_get_status(struct ar5523 *ar, u32 which, void *odata,
int olen)
{
int error;
__be32 which_be;
which_be = cpu_to_be32(which);
error = ar5523_cmd_read(ar, WDCMSG_TARGET_GET_STATUS,
&which_be, sizeof(which_be), odata, olen, AR5523_CMD_FLAG_MAGIC);
if (error != 0)
ar5523_err(ar, "could not read EEPROM offset 0x%02x\n", which);
return error;
}
static int ar5523_get_capability(struct ar5523 *ar, u32 cap, u32 *val)
{
int error;
cap = cpu_to_be32(cap);
error = ar5523_cmd_read(ar, WDCMSG_TARGET_GET_CAPABILITY,
&cap, sizeof(cap), val, sizeof(u32), AR5523_CMD_FLAG_MAGIC);
if (error != 0) {
ar5523_err(ar, "could not read capability %u\n",
be32_to_cpu(cap));
return error;
}
*val = be32_to_cpu(*val);
return error;
}
/*
* Interface routines to the mac80211 stack.
*/
static int ar5523_start(struct ieee80211_hw *hw)
{
struct ar5523 *ar = hw->priv;
int error;
__be32 val;
ar5523_dbg(ar, "start called\n");
mutex_lock(&ar->mutex);
val = cpu_to_be32(0);
ar5523_cmd_write(ar, WDCMSG_BIND, &val, sizeof(val), 0);
/* set MAC address */
ar5523_config_multi(ar, CFG_MAC_ADDR, &ar->hw->wiphy->perm_addr,
ETH_ALEN);
/* XXX honor net80211 state */
ar5523_config(ar, CFG_RATE_CONTROL_ENABLE, 0x00000001);
ar5523_config(ar, CFG_DIVERSITY_CTL, 0x00000001);
ar5523_config(ar, CFG_ABOLT, 0x0000003f);
ar5523_config(ar, CFG_WME_ENABLED, 0x00000000);
ar5523_config(ar, CFG_SERVICE_TYPE, 1);
ar5523_config(ar, CFG_TP_SCALE, 0x00000000);
ar5523_config(ar, CFG_TPC_HALF_DBM5, 0x0000003c);
ar5523_config(ar, CFG_TPC_HALF_DBM2, 0x0000003c);
ar5523_config(ar, CFG_OVERRD_TX_POWER, 0x00000000);
ar5523_config(ar, CFG_GMODE_PROTECTION, 0x00000000);
ar5523_config(ar, CFG_GMODE_PROTECT_RATE_INDEX, 0x00000003);
ar5523_config(ar, CFG_PROTECTION_TYPE, 0x00000000);
ar5523_config(ar, CFG_MODE_CTS, 0x00000002);
error = ar5523_cmd_read(ar, WDCMSG_TARGET_START, NULL, 0,
&val, sizeof(val), AR5523_CMD_FLAG_MAGIC);
if (error) {
ar5523_dbg(ar, "could not start target, error %d\n", error);
goto err;
}
ar5523_dbg(ar, "WDCMSG_TARGET_START returns handle: 0x%x\n",
be32_to_cpu(val));
ar5523_switch_chan(ar);
val = cpu_to_be32(TARGET_DEVICE_AWAKE);
ar5523_cmd_write(ar, WDCMSG_SET_PWR_MODE, &val, sizeof(val), 0);
/* XXX? check */
ar5523_cmd_write(ar, WDCMSG_RESET_KEY_CACHE, NULL, 0, 0);
set_bit(AR5523_HW_UP, &ar->flags);
queue_work(ar->wq, &ar->rx_refill_work);
/* enable Rx */
ar5523_set_rxfilter(ar, 0, UATH_FILTER_OP_INIT);
ar5523_set_rxfilter(ar,
UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST |
UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON,
UATH_FILTER_OP_SET);
ar5523_set_ledsteady(ar, UATH_LED_ACTIVITY, UATH_LED_ON);
ar5523_dbg(ar, "start OK\n");
err:
mutex_unlock(&ar->mutex);
return error;
}
