static int cpmac_mdio_reset(struct mii_bus *bus)
{
ar7_device_reset(AR7_RESET_BIT_MDIO);
cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
return 0;
}
static int cpmac_mdio_reset(struct mii_bus *bus)
{
struct clk *cpmac_clk;
cpmac_clk = clk_get(&bus->dev, "cpmac");
if (IS_ERR(cpmac_clk)) {
printk(KERN_ERR "unable to get cpmac clock\n");
return -1;
}
ar7_device_reset(AR7_RESET_BIT_MDIO);
cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
return 0;
}
//static int cpmac_open(struct net_device *dev);
//
//static void cpmac_dump_regs(struct net_device *dev)
//{
// int i;
// struct cpmac_priv *priv = netdev_priv(dev);
//
// for (i = 0; i < CPMAC_REG_END; i += 4) {
// if (i % 16 == 0) {
// if (i)
// printk("\n");
// printk("%s: reg[%p]:", dev->name, priv->regs + i);
// }
// printk(" %08x", cpmac_read(priv->regs, i));
// }
// printk("\n");
//}
//
//static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
//{
// int i;
//
// printk("%s: desc[%p]:", dev->name, desc);
// for (i = 0; i < sizeof(*desc) / 4; i++)
// printk(" %08x", ((u32 *)desc)[i]);
// printk("\n");
//}
//
//static void cpmac_dump_all_desc(struct net_device *dev)
//{
// struct cpmac_priv *priv = netdev_priv(dev);
// struct cpmac_desc *dump = priv->rx_head;
//
// do {
// cpmac_dump_desc(dev, dump);
// dump = dump->next;
// } while (dump != priv->rx_head);
//}
//
//static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
//{
// int i;
//
// printk("%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
// for (i = 0; i < skb->len; i++) {
// if (i % 16 == 0) {
// if (i)
// printk("\n");
// printk("%s: data[%p]:", dev->name, skb->data + i);
// }
// printk(" %02x", ((u8 *)skb->data)[i]);
// }
// printk("\n");
//}
//
//static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
//{
// u32 val;
//
// while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
// cpu_relax();
// cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
// MDIO_PHY(phy_id));
// while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
// cpu_relax();
//
// return MDIO_DATA(val);
//}
//
//static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
// int reg, u16 val)
//{
// while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
// cpu_relax();
// cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
// MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
//
// return 0;
//}
//
static int cpmac_mdio_reset()
{
// struct clk *cpmac_clk;
// cpmac_clk = clk_get("cpmac");
// if (IS_ERR(cpmac_clk)) {
// pr_err("unable to get cpmac clock\n");
// return -1;
// }
ar7_device_reset(AR7_RESET_BIT_MDIO);
cpmac_write(CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
MDIOC_CLKDIV(/*clk_get_rate(cpmac_clk)*/nondet / 2200000 - 1));
return 0;
}
static void cpmac_hw_start()
{
int i;
//struct cpmac_priv *priv = netdev_priv(dev);
//struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
ar7_device_reset(pdata.reset_bit);
//for (i = 0; i < 8; i++) {
cpmac_write(CPMAC_TX_PTR(i), 0);
lock_s(synthlock_0);
cpmac_write_CPMAC_RX_PTR(i, 0);
//}
cpmac_write_CPMAC_RX_PTR(0, rx_head->mapping);
cpmac_write(CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
MBP_RXMCAST);
cpmac_write(CPMAC_BUFFER_OFFSET, 0);
//for (i = 0; i < 8; i++)
cpmac_write(CPMAC_MAC_ADDR_LO(i), netdev.dev_addr[5]);
cpmac_write(CPMAC_MAC_ADDR_MID, netdev.dev_addr[4]);
cpmac_write(CPMAC_MAC_ADDR_HI, netdev.dev_addr[0] |
(netdev.dev_addr[1] << 8) | (netdev.dev_addr[2] << 16) |
(netdev.dev_addr[3] << 24));
cpmac_write(CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
cpmac_write(CPMAC_UNICAST_CLEAR, 0xff);
cpmac_write(CPMAC_RX_INT_CLEAR, 0xff);
cpmac_write(CPMAC_TX_INT_CLEAR, 0xff);
cpmac_write(CPMAC_MAC_INT_CLEAR, 0xff);
cpmac_write(CPMAC_UNICAST_ENABLE, 1);
cpmac_write(CPMAC_RX_INT_ENABLE, 1);
cpmac_write(CPMAC_TX_INT_ENABLE, 0xff);
cpmac_write(CPMAC_MAC_INT_ENABLE, 3);
cpmac_write(CPMAC_RX_CONTROL,
cpmac_read(CPMAC_RX_CONTROL) | 1);
cpmac_write(CPMAC_TX_CONTROL,
cpmac_read(CPMAC_TX_CONTROL) | 1);
cpmac_write(CPMAC_MAC_CONTROL,
cpmac_read(CPMAC_MAC_CONTROL) | MAC_MII |
MAC_FDX);
unlock_s(synthlock_0);
}
static void cpmac_hw_start(struct net_device *dev)
{
int i;
struct cpmac_priv *priv = netdev_priv(dev);
struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
ar7_device_reset(pdata->reset_bit);
for (i = 0; i < 8; i++) {
cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
}
cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
MBP_RXMCAST);
cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
for (i = 0; i < 8; i++)
cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
(dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
(dev->dev_addr[3] << 24));
cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
cpmac_write(priv->regs, CPMAC_RX_CONTROL,
cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
cpmac_write(priv->regs, CPMAC_TX_CONTROL,
cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
MAC_FDX);
}
static int vlynq_on(struct vlynq_device *dev)
{
int ret;
struct plat_vlynq_data *pdata = dev->dev.platform_data;
ret = gpio_request(pdata->gpio_bit, "vlynq");
if (ret)
goto out;
ar7_device_reset(pdata->reset_bit);
ret = ar7_gpio_disable(pdata->gpio_bit);
if (ret)
goto out_enabled;
ret = ar7_gpio_enable(pdata->gpio_bit);
if (ret)
goto out_enabled;
ret = gpio_direction_output(pdata->gpio_bit, 0);
if (ret)
goto out_gpio_enabled;
msleep(50);
gpio_set_value(pdata->gpio_bit, 1);
msleep(50);
return 0;
out_gpio_enabled:
ar7_gpio_disable(pdata->gpio_bit);
out_enabled:
ar7_device_disable(pdata->reset_bit);
gpio_free(pdata->gpio_bit);
out:
return ret;
}
static void cpmac_hw_stop(/*struct net_device *dev*/)
{
int i;
//struct cpmac_priv *priv = netdev_priv(dev);
//struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
ar7_device_reset(pdata.reset_bit);
cpmac_write(CPMAC_RX_CONTROL,
cpmac_read(CPMAC_RX_CONTROL) & ~1);
cpmac_write(CPMAC_TX_CONTROL,
cpmac_read(CPMAC_TX_CONTROL) & ~1);
//for (i = 0; i < 8; i++) {
cpmac_write(CPMAC_TX_PTR(i), 0);
cpmac_write_CPMAC_RX_PTR(i, 0);
//}
cpmac_write(CPMAC_UNICAST_CLEAR, 0xff);
cpmac_write(CPMAC_RX_INT_CLEAR, 0xff);
cpmac_write(CPMAC_TX_INT_CLEAR, 0xff);
cpmac_write(CPMAC_MAC_INT_CLEAR, 0xff);
cpmac_write(CPMAC_MAC_CONTROL,
cpmac_read(CPMAC_MAC_CONTROL) & ~MAC_MII);
}
static void cpmac_hw_stop(struct net_device *dev)
{
int i;
struct cpmac_priv *priv = netdev_priv(dev);
struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
ar7_device_reset(pdata->reset_bit);
cpmac_write(priv->regs, CPMAC_RX_CONTROL,
cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
cpmac_write(priv->regs, CPMAC_TX_CONTROL,
cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
for (i = 0; i < 8; i++) {
cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
}
cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
}
