ir_node *be_new_Perm(arch_register_class_t const *const cls,
ir_node *const block, int const n,
ir_node *const *const in)
{
ir_graph *irg = get_irn_irg(block);
ir_node *irn = new_ir_node(NULL, irg, block, op_be_Perm, mode_T, n, in);
init_node_attr(irn, n, arch_irn_flags_none);
be_node_attr_t *attr = (be_node_attr_t*)get_irn_generic_attr(irn);
attr->exc.pin_state = op_pin_state_pinned;
for (int i = 0; i < n; ++i) {
const ir_node *input = in[i];
const arch_register_req_t *req = arch_get_irn_register_req(input);
if (req->width == 1) {
be_node_set_register_req_in(irn, i, cls->class_req);
arch_set_irn_register_req_out(irn, i, cls->class_req);
} else {
arch_register_req_t *const new_req = allocate_reg_req(irg);
new_req->cls = cls;
new_req->width = req->width;
new_req->aligned = req->aligned;
be_node_set_register_req_in(irn, i, new_req);
arch_set_irn_register_req_out(irn, i, new_req);
}
}
return irn;
}
static void set_copy_info(ir_node *const irn, ir_graph *const irg, ir_node *const op, arch_irn_flags_t const flags)
{
init_node_attr(irn, 1, flags);
arch_register_req_t const *const op_req = arch_get_irn_register_req(op);
arch_register_class_t const *const cls = op_req->cls;
be_node_set_register_req_in(irn, 0, cls->class_req);
arch_register_req_t *const out_req = be_create_cls_req(irg, cls, op_req->width);
out_req->should_be_same = 1U << 0;
arch_set_irn_register_req_out(irn, 0, out_req);
}
ir_node *be_new_Keep(ir_node *const block, int const n,
ir_node *const *const in)
{
ir_graph *irg = get_irn_irg(block);
ir_node *res = new_ir_node(NULL, irg, block, op_be_Keep, mode_ANY, n, in);
init_node_attr(res, 1, arch_irn_flag_schedule_first);
for (int i = 0; i < n; ++i) {
arch_register_req_t const *const req = arch_get_irn_register_req(in[i]);
be_node_set_register_req_in(res, i, req->cls->class_req);
}
keep_alive(res);
return res;
}
ir_node *be_new_Perm(ir_node *const block, int const n, ir_node *const *const in)
{
ir_graph *const irg = get_irn_irg(block);
ir_node *const irn = new_ir_node(NULL, irg, block, op_be_Perm, mode_T, n, in);
init_node_attr(irn, n, arch_irn_flags_none);
for (int i = 0; i < n; ++i) {
arch_register_req_t const *const in_req = arch_get_irn_register_req(in[i]);
arch_register_req_t const *const slot_req =
in_req->width == 1 ? in_req->cls->class_req :
be_create_cls_req(irg, in_req->cls, in_req->width);
be_node_set_register_req_in( irn, i, slot_req);
arch_set_irn_register_req_out(irn, i, slot_req);
}
return irn;
}
ir_node *be_new_CopyKeep(ir_node *const bl, ir_node *const src, int const n, ir_node *const *const in_keep)
{
ir_mode *mode = get_irn_mode(src);
ir_graph *irg = get_irn_irg(bl);
int arity = n+1;
ir_node **in = ALLOCAN(ir_node*, arity);
in[0] = src;
MEMCPY(&in[1], in_keep, n);
ir_node *irn = new_ir_node(NULL, irg, bl, op_be_CopyKeep, mode, arity, in);
set_copy_info(irn, irg, src, arch_irn_flag_schedule_first);
for (int i = 0; i < n; ++i) {
ir_node *pred = in_keep[i];
arch_register_req_t const *const req = arch_get_irn_register_req(pred);
be_node_set_register_req_in(irn, i + 1, req->cls->class_req);
}
return irn;
}
ir_node *be_new_Keep(ir_node *const block, int const n,
ir_node *const *const in)
{
ir_graph *irg = get_irn_irg(block);
ir_node *res = new_ir_node(NULL, irg, block, op_be_Keep, mode_ANY, n, in);
init_node_attr(res, 1, arch_irn_flag_schedule_first);
be_node_attr_t *attr = (be_node_attr_t*) get_irn_generic_attr(res);
attr->exc.pin_state = op_pin_state_pinned;
for (int i = 0; i < n; ++i) {
arch_register_req_t const *req = arch_get_irn_register_req(in[i]);
req = req->cls != NULL ? req->cls->class_req : arch_no_register_req;
be_node_set_register_req_in(res, i, req);
}
keep_alive(res);
return res;
}
ir_node *be_new_IncSP(ir_node *bl, ir_node *old_sp, int offset, bool no_align)
{
arch_register_class_t const *const cls = arch_get_irn_register_req(old_sp)->cls;
ir_graph *irg = get_irn_irg(bl);
ir_node *in[] = { old_sp };
ir_node *irn = new_ir_node(NULL, irg, bl, op_be_IncSP, cls->mode,
ARRAY_SIZE(in), in);
init_node_attr(irn, 1, arch_irn_flags_none);
be_incsp_attr_t *a = (be_incsp_attr_t*)get_irn_generic_attr(irn);
a->offset = offset;
a->no_align = no_align;
/* Set output constraint to stack register. */
be_node_set_register_req_in(irn, 0, cls->class_req);
arch_copy_irn_out_info(irn, 0, old_sp);
return irn;
}
static void set_copy_info(ir_node *const irn, ir_graph *const irg, ir_node *const op, arch_irn_flags_t const flags)
{
init_node_attr(irn, 1, flags);
be_node_attr_t *const attr = (be_node_attr_t*)get_irn_generic_attr(irn);
attr->exc.pin_state = op_pin_state_floats;
arch_register_req_t const *const op_req = arch_get_irn_register_req(op);
arch_register_class_t const *const cls = op_req->cls;
be_node_set_register_req_in(irn, 0, cls->class_req);
arch_register_req_t *const out_req = allocate_reg_req(irg);
out_req->cls = cls;
out_req->should_be_same = 1U << 0;
out_req->aligned = op_req->aligned;
out_req->width = op_req->width;
arch_set_irn_register_req_out(irn, 0, out_req);
}
ir_node *be_complete_Phi(ir_node *const phi, unsigned const n_ins, ir_node **const ins)
{
assert(is_Phi(phi) && get_Phi_n_preds(phi) == 0);
ir_graph *const irg = get_irn_irg(phi);
phi->attr.phi.u.backedge = new_backedge_arr(get_irg_obstack(irg), n_ins);
set_irn_in(phi, n_ins, ins);
arch_register_req_t const **const in_reqs = be_allocate_in_reqs(irg, n_ins);
arch_register_req_t const *const req = arch_get_irn_register_req(phi);
for (unsigned i = 0; i < n_ins; ++i) {
in_reqs[i] = req;
}
backend_info_t *const info = be_get_info(phi);
info->in_reqs = in_reqs;
verify_new_node(phi);
return phi;
}
