void platform_early_init(void)
{
ps7_init();
/* zynq manual says this is mandatory */
*REG32(SLCR_BASE + 0xa1c) = 0x020202;
/* early initialize the uart so we can printf */
uart_init_early();
/* initialize the interrupt controller */
arm_gic_init();
/* initialize the timer block */
arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq());
/* add the main memory arena */
#if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0
/* In the case of running from SRAM, and we are using SDRAM,
* there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB),
* so intentionally bump the boot-time allocator to start in the base of SDRAM.
*/
extern uintptr_t boot_alloc_start;
extern uintptr_t boot_alloc_end;
boot_alloc_start = KERNEL_BASE + MB;
boot_alloc_end = KERNEL_BASE + MB;
#endif
#if SDRAM_SIZE != 0
pmm_add_arena(&sdram_arena);
#endif
pmm_add_arena(&sram_arena);
}
void plat_mt_gic_init(void)
{
arm_gic_init(BASE_GICC_BASE,
BASE_GICD_BASE,
BASE_GICR_BASE,
mt_irq_sec_array,
ARRAY_SIZE(mt_irq_sec_array));
}
void plat_gic_init(void)
{
arm_gic_init(GICC_BASE,
GICD_BASE,
0,
irq_sec_array,
ARRAY_SIZE(irq_sec_array));
}
void platform_early_init(void)
{
/* initialize the interrupt controller */
arm_gic_init();
arm_generic_timer_init(ARM_GENERIC_TIMER_PHYSICAL_INT, 0);
uart_init_early();
/* look for a flattened device tree just before the kernel */
const void *fdt = (void *)KERNEL_BASE;
int err = fdt_check_header(fdt);
if (err >= 0) {
/* walk the nodes, looking for 'memory' */
int depth = 0;
int offset = 0;
for (;;) {
offset = fdt_next_node(fdt, offset, &depth);
if (offset < 0)
break;
/* get the name */
const char *name = fdt_get_name(fdt, offset, NULL);
if (!name)
continue;
/* look for the 'memory' property */
if (strcmp(name, "memory") == 0) {
int lenp;
const void *prop_ptr = fdt_getprop(fdt, offset, "reg", &lenp);
if (prop_ptr && lenp == 0x10) {
/* we're looking at a memory descriptor */
//uint64_t base = fdt64_to_cpu(*(uint64_t *)prop_ptr);
uint64_t len = fdt64_to_cpu(*((const uint64_t *)prop_ptr + 1));
/* trim size on certain platforms */
#if ARCH_ARM
if (len > 1024*1024*1024U) {
len = 1024*1024*1024; /* only use the first 1GB on ARM32 */
printf("trimming memory to 1GB\n");
}
#endif
/* set the size in the pmm arena */
arena.size = len;
}
}
}
}
/* add the main memory arena */
pmm_add_arena(&arena);
/* reserve the first 64k of ram, which should be holding the fdt */
struct list_node list = LIST_INITIAL_VALUE(list);
pmm_alloc_range(MEMBASE, 0x10000 / PAGE_SIZE, &list);
}
void platform_early_init(void)
{
/* initialize the interrupt controller */
arm_gic_init();
/* initialize the timer block */
arm_cortex_a9_timer_init(CPUPRIV_BASE_PHYS, 100000000);
uart_init_early();
/* add the main memory arena */
pmm_add_arena(&arena);
}
void platform_early_init(void)
{
zynq_mio_init();
zynq_pll_init();
zynq_clk_init();
#if ZYNQ_SDRAM_INIT
zynq_ddr_init();
#endif
zynq_slcr_unlock();
/* Enable all level shifters */
SLCR_REG(LVL_SHFTR_EN) = 0xF;
/* FPGA SW reset (not documented, but mandatory) */
SLCR_REG(FPGA_RST_CTRL) = 0x0;
/* zynq manual says this is mandatory for cache init */
*REG32(SLCR_BASE + 0xa1c) = 0x020202;
zynq_slcr_lock();
/* early initialize the uart so we can printf */
uart_init_early();
/* initialize the interrupt controller */
arm_gic_init();
/* initialize the timer block */
arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq());
/* add the main memory arena */
#if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0
/* In the case of running from SRAM, and we are using SDRAM,
* there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB),
* so intentionally bump the boot-time allocator to start in the base of SDRAM.
*/
extern uintptr_t boot_alloc_start;
extern uintptr_t boot_alloc_end;
boot_alloc_start = KERNEL_BASE + MB;
boot_alloc_end = KERNEL_BASE + MB;
#endif
#if SDRAM_SIZE != 0
pmm_add_arena(&sdram_arena);
#endif
pmm_add_arena(&sram_arena);
}
void platform_early_init(void)
{
#if 0
ps7_init();
#else
/* Unlock the registers and leave them that way */
zynq_slcr_unlock();
zynq_mio_init();
zynq_pll_init();
zynq_clk_init();
#if ZYNQ_SDRAM_INIT
zynq_ddr_init();
#endif
#endif
/* Enable all level shifters */
SLCR_REG(LVL_SHFTR_EN) = 0xF;
/* FPGA SW reset (not documented, but mandatory) */
SLCR_REG(FPGA_RST_CTRL) = 0x0;
/* zynq manual says this is mandatory for cache init */
*REG32(SLCR_BASE + 0xa1c) = 0x020202;
/* early initialize the uart so we can printf */
uart_init_early();
/* initialize the interrupt controller */
arm_gic_init();
zynq_gpio_init();
/* initialize the timer block */
arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq());
/* bump the 2nd cpu into our code space and remap the top SRAM block */
if (KERNEL_LOAD_OFFSET != 0) {
/* construct a trampoline to get the 2nd cpu up to the trap routine */
/* figure out the offset of the trampoline routine in physical space from address 0 */
extern void platform_reset(void);
addr_t tramp = (addr_t)&platform_reset;
tramp -= KERNEL_BASE;
tramp += MEMBASE;
/* stuff in a ldr pc, [nextaddrress], and a target address */
uint32_t *ptr = (uint32_t *)KERNEL_BASE;
ptr[0] = 0xe51ff004; // ldr pc, [pc, #-4]
ptr[1] = tramp;
arch_clean_invalidate_cache_range((addr_t)ptr, 8);
}
/* reset the 2nd cpu, letting it go through its reset vector (at 0x0 physical) */
SLCR_REG(A9_CPU_RST_CTRL) |= (1<<1); // reset cpu 1
spin(10);
SLCR_REG(A9_CPU_RST_CTRL) &= ~(1<<1); // unreset cpu 1
/* wait for the 2nd cpu to reset, go through the usual reset vector, and get trapped by our code */
/* see platform/zynq/reset.S */
extern volatile int __cpu_trapped;
uint count = 100000;
while (--count) {
arch_clean_invalidate_cache_range((addr_t)&__cpu_trapped, sizeof(__cpu_trapped));
if (__cpu_trapped != 0)
break;
}
if (count == 0) {
panic("ZYNQ: failed to trap 2nd cpu\n");
}
/* bounce the 4th sram region down to lower address */
SLCR_REG(OCM_CFG) &= ~0xf; /* all banks at low address */
/* add the main memory arena */
#if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0
/* In the case of running from SRAM, and we are using SDRAM,
* there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB),
* so intentionally bump the boot-time allocator to start in the base of SDRAM.
*/
extern uintptr_t boot_alloc_start;
extern uintptr_t boot_alloc_end;
boot_alloc_start = KERNEL_BASE + MB;
boot_alloc_end = KERNEL_BASE + MB;
#endif
#if SDRAM_SIZE != 0
pmm_add_arena(&sdram_arena);
#endif
pmm_add_arena(&sram_arena);
}
static void realview_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
CPUState *env;
void *pic;
void *scsi_hba;
PCIBus *pci_bus;
NICInfo *nd;
int n;
int done_smc = 0;
env = cpu_init();
cpu_arm_set_model(env, ARM_CPUID_ARM926);
//cpu_arm_set_model(env, ARM_CPUID_ARM11MPCORE);
/* ??? RAM shoud repeat to fill physical memory space. */
/* SDRAM at address zero. */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
arm_sysctl_init(0x10000000, 0xc1400400);
pic = arm_pic_init_cpu(env);
/* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3
is nIRQ (there are inconsistencies). However Linux 2.6.17 expects
GIC1 to be nIRQ and ignores all the others, so do that for now. */
pic = arm_gic_init(0x10040000, pic, ARM_PIC_CPU_IRQ);
pl050_init(0x10006000, pic, 20, 0);
pl050_init(0x10007000, pic, 21, 1);
pl011_init(0x10009000, pic, 12, serial_hds[0]);
pl011_init(0x1000a000, pic, 13, serial_hds[1]);
pl011_init(0x1000b000, pic, 14, serial_hds[2]);
pl011_init(0x1000c000, pic, 15, serial_hds[3]);
/* DMA controller is optional, apparently. */
pl080_init(0x10030000, pic, 24, 2);
sp804_init(0x10011000, pic, 4);
sp804_init(0x10012000, pic, 5);
pl110_init(ds, 0x10020000, pic, 23, 1);
pci_bus = pci_vpb_init(pic, 48, 1);
if (usb_enabled) {
usb_ohci_init(pci_bus, 3, -1);
}
scsi_hba = lsi_scsi_init(pci_bus, -1);
for (n = 0; n < MAX_DISKS; n++) {
if (bs_table[n]) {
lsi_scsi_attach(scsi_hba, bs_table[n], n);
}
}
for(n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = done_smc ? "rtl8139" : "smc91c111";
if (strcmp(nd->model, "smc91c111") == 0) {
smc91c111_init(nd, 0x4e000000, pic, 28);
} else {
pci_nic_init(pci_bus, nd, -1);
}
}
/* Memory map for RealView Emulation Baseboard: */
/* 0x10000000 System registers. */
/* 0x10001000 System controller. */
/* 0x10002000 Two-Wire Serial Bus. */
/* 0x10003000 Reserved. */
/* 0x10004000 AACI. */
/* 0x10005000 MCI. */
/* 0x10006000 KMI0. */
/* 0x10007000 KMI1. */
/* 0x10008000 Character LCD. */
/* 0x10009000 UART0. */
/* 0x1000a000 UART1. */
/* 0x1000b000 UART2. */
/* 0x1000c000 UART3. */
/* 0x1000d000 SSPI. */
/* 0x1000e000 SCI. */
/* 0x1000f000 Reserved. */
/* 0x10010000 Watchdog. */
/* 0x10011000 Timer 0+1. */
/* 0x10012000 Timer 2+3. */
/* 0x10013000 GPIO 0. */
/* 0x10014000 GPIO 1. */
/* 0x10015000 GPIO 2. */
/* 0x10016000 Reserved. */
/* 0x10017000 RTC. */
/* 0x10018000 DMC. */
/* 0x10019000 PCI controller config. */
/* 0x10020000 CLCD. */
/* 0x10030000 DMA Controller. */
/* 0x10040000 GIC1 (FIQ1). */
/* 0x10050000 GIC2 (IRQ1). */
/* 0x10060000 GIC3 (FIQ2). */
/* 0x10070000 GIC4 (IRQ2). */
/* 0x10080000 SMC. */
/* 0x40000000 NOR flash. */
/* 0x44000000 DoC flash. */
/* 0x48000000 SRAM. */
/* 0x4c000000 Configuration flash. */
/* 0x4e000000 Ethernet. */
/* 0x4f000000 USB. */
/* 0x50000000 PISMO. */
/* 0x54000000 PISMO. */
/* 0x58000000 PISMO. */
/* 0x5c000000 PISMO. */
/* 0x60000000 PCI. */
/* 0x61000000 PCI Self Config. */
/* 0x62000000 PCI Config. */
/* 0x63000000 PCI IO. */
/* 0x64000000 PCI mem 0. */
/* 0x68000000 PCI mem 1. */
/* 0x6c000000 PCI mem 2. */
arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
initrd_filename, 0x33b);
}
