/*
* Generic second stage pbl uncompressor entry
*/
ENTRY_FUNCTION(start_uncompress)(uint32_t membase, uint32_t memsize,
uint32_t boarddata)
{
arm_setup_stack(membase + memsize - 16);
uncompress(membase, memsize, boarddata);
}
/*
* Main ARM entry point in the compressed image. Call this with the memory
* region you can spare for barebox. This doesn't necessarily have to be the
* full SDRAM. The currently running binary can be inside or outside of this
* region. TEXT_BASE can be inside or outside of this region. boarddata will
* be preserved and can be accessed later with barebox_arm_boarddata().
*
* -> membase + memsize
* STACK_SIZE - stack
* 16KiB, aligned to 16KiB - First level page table if early MMU support
* is enabled
* 128KiB - early memory space
* -> maximum end of barebox binary
*
* Usually a TEXT_BASE of 1MiB below your lowest possible end of memory should
* be fine.
*/
void __naked __noreturn barebox_arm_entry(uint32_t membase, uint32_t memsize,
uint32_t boarddata)
{
arm_setup_stack(membase + memsize - 16);
__barebox_arm_entry(membase, memsize, boarddata);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), 0);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
at91sam9261_lowlevel_init();
}
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
{
arm_cpu_lowlevel_init();
arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
usb_a9263_init();
}
ENTRY_FUNCTION(start_socfpga_socrates_xload, r0, r1, r2)
{
arm_cpu_lowlevel_init();
arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16);
socrates_entry();
}
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
{
arm_cpu_lowlevel_init();
arm_setup_stack(AT91SAM9N12_SRAM_BASE + AT91SAM9N12_SRAM_SIZE - 16);
barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9n12_get_ddram_size(),
NULL);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);
barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
NULL);
}
void __bare_init __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
/* Temporary stack location in internal SRAM */
arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8);
mx31moboard_startup();
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
barebox_arm_entry(AT91_CHIPSELECT_1,
at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
NULL);
}
ENTRY_FUNCTION(start_imx53_vmx53, r0, r1, r2)
{
void *fdt;
imx5_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
fdt = __dtb_imx53_voipac_bsb_start - get_runtime_offset();
imx53_barebox_entry(fdt);
}
ENTRY_FUNCTION(start_imx6_wandboard, r0, r1, r2)
{
imx6_cpu_lowlevel_init();
arm_setup_stack(0x0091ffb0);
relocate_to_current_adr();
setup_c();
barrier();
wandboard_start();
}
void barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
if (get_pc() > 0x80000000)
goto out;
arm_setup_stack(0x4030d000);
pcm049_init_lowlevel();
out:
barebox_arm_entry(0x80000000, SZ_512M, 0);
}
void __naked __noreturn barebox_arm_entry(unsigned long membase,
unsigned long memsize, void *boarddata)
{
arm_setup_stack(arm_mem_stack(membase, membase + memsize) + STACK_SIZE - 16);
arm_early_mmu_cache_invalidate();
if (IS_ENABLED(CONFIG_PBL_MULTI_IMAGES))
barebox_multi_pbl_start(membase, memsize, boarddata);
else if (IS_ENABLED(CONFIG_PBL_SINGLE_IMAGE))
barebox_single_pbl_start(membase, memsize, boarddata);
else
barebox_non_pbl_start(membase, memsize, boarddata);
}
ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2)
{
extern char __dtb_imx51_ccxmx51_start[];
void *fdt;
imx5_cpu_lowlevel_init();
arm_setup_stack(0x20000000 - 16);
fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset();
barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt);
}
ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2)
{
uint32_t fdt;
__barebox_arm_head();
arm_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();
barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt);
}
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
imx53_init_lowlevel_early(800);
fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
ENTRY_FUNCTION(start_variscite_custom, r0, r1, r2)
{
void *fdt;
imx6_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
fdt = __dtb_imx6q_var_custom_start + get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
void __naked barebox_arm_reset_vector(void)
{
imx5_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
/*
* For the TX53 rev 8030 the SDRAM setup is not stable without
* the proper PLL setup. It will crash once we enable the MMU,
* so do the PLL setup here.
*/
if (IS_ENABLED(CONFIG_TX53_REV_XX30))
imx53_init_lowlevel_early(800);
imx53_barebox_entry(NULL);
}
static void __noreturn start_imx6q_phytec_pbaa03_common(uint32_t size)
{
void *fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
fdt = __dtb_imx6q_phytec_pbaa03_start - get_runtime_offset();
barebox_arm_entry(0x10000000, size, fdt);
}
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
omap4_save_bootinfo(data);
arm_cpu_lowlevel_init();
if (get_pc() > 0x80000000)
goto out;
arm_setup_stack(0x4030d000);
pcaaxl2_init_lowlevel();
out:
barebox_arm_entry(0x80000000, SZ_512M, 0);
}
ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2)
{
uint32_t fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_2G, fdt);
}
ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q)(void)
{
uint32_t fdt;
__barebox_arm_head();
arm_cpu_lowlevel_init();
arm_setup_stack(0x00940000 - 8);
early_uart_init_6q();
fdt = (uint32_t)__dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
void *fdt;
arm_cpu_lowlevel_init();
arm_setup_stack(0xf8020000 - 8);
IMD_USED(tqma53_memsize_1G);
imx53_init_lowlevel_early(800);
fdt = __dtb_imx53_mba53_start - get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
void *fdt;
imx5_cpu_lowlevel_init();
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
IMD_USED(tqma53_memsize_1G);
imx53_init_lowlevel_early(800);
fdt = __dtb_imx53_mba53_start + get_runtime_offset();
start_imx53_tqma53_common(fdt);
}
static void __noreturn start_imx6_phytec_common(uint32_t size,
bool do_early_uart_config,
void *fdt_blob_fixed_offset)
{
void *fdt;
imx6_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
fdt = fdt_blob_fixed_offset - get_runtime_offset();
barebox_arm_entry(0x10000000, size, fdt);
}
ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2)
{
void *fdt;
int i;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
for (i = 0x68; i <= 0x80; i += 4)
writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
early_uart_init_6s();
fdt = __dtb_imx6dl_dfi_fs700_m60_6s_start - get_runtime_offset();
barebox_arm_entry(0x10000000, memsize_512M_1G(), fdt);
}
ENTRY_FUNCTION(start_imx6q_guf_santaro, r0, r1, r2)
{
uint32_t fdt;
int i;
arm_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
for (i = 0x68; i <= 0x80; i += 4)
writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
setup_uart();
fdt = (uint32_t)__dtb_imx6q_guf_santaro_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
static noinline void imx53_guf_vincell_init(int is_lt)
{
void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR;
void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR);
void *fdt;
u32 r;
enum bootsource src;
int instance;
arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
writel(0x0088494c, ccm + MX5_CCM_CBCDR);
writel(0x02b12f0a, ccm + MX5_CCM_CSCMR2);
imx53_ungate_all_peripherals();
imx53_init_lowlevel_early(800);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c);
writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278);
imx53_uart_setup(uart);
pbl_set_putc(imx_uart_putc, uart);
pr_debug("GuF Vincell\n");
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (!(r > 0x70000000 && r < 0xf0000000)) {
disable_watchdog();
configure_dram_iomux();
imx_esdctlv4_init();
imx53_get_boot_source(&src, &instance);
if (src == BOOTSOURCE_NAND &&
IS_ENABLED(CONFIG_MACH_GUF_VINCELL_XLOAD))
imx53_nand_start_image();
}
if (is_lt)
fdt = __dtb_imx53_guf_vincell_lt_start;
else
fdt = __dtb_imx53_guf_vincell_start;
imx53_barebox_entry(fdt);
}
void __bare_init __naked barebox_arm_reset_vector(void)
{
unsigned long r;
arm_cpu_lowlevel_init();
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0xa0000000 && r < 0xc0000000)
imx27_barebox_entry(0);
/* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0);
/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0);
writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
sdram_init();
imx27_barebox_boot_nand_external(0);
}
