static void usb_eye_configure(u32 set, u32 clear) { u32 old; old = asic_read(crt_spare); old |= set; old &= ~clear; asic_write(old, crt_spare); }
static inline void mask_asic_irq(unsigned int irq) { unsigned long disable_mask; disable_mask = ~(1 << (irq & 0x1f)); switch (irq >> 5) { case 0: asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0); break; case 1: asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1); break; case 2: asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2); break; case 3: asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3); break; default: BUG(); } }
static inline void unmask_asic_irq(unsigned int irq) { unsigned long enable_bit; enable_bit = (1 << (irq & 0x1f)); switch (irq >> 5) { case 0: asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0); break; case 1: asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1); break; case 2: asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2); break; case 3: asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3); break; default: BUG(); } }
/* * returns: Clock frequency in kHz */ unsigned int __init mips_get_pll_freq(void) { unsigned int pll_reg, m, n, p; unsigned int fin = 54000; /* Base frequency in kHz */ unsigned int fout; /* Read PLL register setting */ pll_reg = asic_read(mips_pll_setup); m = PLL_GET_M(pll_reg); n = PLL_GET_N(pll_reg); p = PLL_GET_P(pll_reg); pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ fout = ((2 * n * fin) / (m * (0x01 << p))); pr_info("MIPS Clock Freq=%d kHz\n", fout); return fout; }
/** * configure_platform - configuration based on platform type. */ void __init configure_platform(void) { platform_set_family(); switch (platform_family) { case FAMILY_1500: case FAMILY_1500VZE: case FAMILY_1500VZF: platform_features = FFS_CAPABLE; asic = ASIC_CALLIOPE; set_register_map(CALLIOPE_IO_BASE, &calliope_register_map); if (platform_family == FAMILY_1500VZE) { gp_resources = non_dvr_vze_calliope_resources; pr_info("Platform: 1500/Vz Class E - " "CALLIOPE, NON_DVR_CAPABLE\n"); } else if (platform_family == FAMILY_1500VZF) { gp_resources = non_dvr_vzf_calliope_resources; pr_info("Platform: 1500/Vz Class F - " "CALLIOPE, NON_DVR_CAPABLE\n"); } else { gp_resources = non_dvr_calliope_resources; pr_info("Platform: 1500/RNG100 - CALLIOPE, " "NON_DVR_CAPABLE\n"); } break; case FAMILY_4500: platform_features = FFS_CAPABLE | PCIE_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_ZEUS; set_register_map(ZEUS_IO_BASE, &zeus_register_map); gp_resources = non_dvr_zeus_resources; pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); break; case FAMILY_4600: { unsigned int chipversion = 0; /* The settop has PCIE but it isn't used, so don't advertise * it*/ platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; /* Cronus and Cronus Lite have the same register map */ set_register_map(CRONUS_IO_BASE, &cronus_register_map); /* ASIC version will determine if this is a real CronusLite or * Castrati(Cronus) */ chipversion = asic_read(chipver3) << 24; chipversion |= asic_read(chipver2) << 16; chipversion |= asic_read(chipver1) << 8; chipversion |= asic_read(chipver0); if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) asic = ASIC_CRONUS; else asic = ASIC_CRONUSLITE; gp_resources = non_dvr_cronuslite_resources; pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " "chipversion=0x%08X\n", (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", chipversion); break; } case FAMILY_4600VZA: platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_CRONUS; set_register_map(CRONUS_IO_BASE, &cronus_register_map); gp_resources = non_dvr_cronus_resources; pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); break; case FAMILY_8500: case FAMILY_8500RNG: platform_features = DVR_CAPABLE | PCIE_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_ZEUS; set_register_map(ZEUS_IO_BASE, &zeus_register_map); gp_resources = dvr_zeus_resources; pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n"); break; case FAMILY_8600: case FAMILY_8600VZB: platform_features = DVR_CAPABLE | PCIE_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_CRONUS; set_register_map(CRONUS_IO_BASE, &cronus_register_map); gp_resources = dvr_cronus_resources; pr_info("Platform: 8600/Vz Class B - CRONUS, " "DVR_CAPABLE\n"); break; case FAMILY_8700: platform_features = FFS_CAPABLE | PCIE_CAPABLE; asic = ASIC_GAIA; set_register_map(GAIA_IO_BASE, &gaia_register_map); gp_resources = dvr_gaia_resources; pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n"); break; default: pr_crit("Platform: UNKNOWN PLATFORM\n"); break; } switch (asic) { case ASIC_ZEUS: phys_to_dma_offset = 0x30000000; break; case ASIC_CALLIOPE: phys_to_dma_offset = 0x10000000; break; case ASIC_CRONUSLITE: /* Fall through */ case ASIC_CRONUS: /* * TODO: We suppose 0x10000000 aliases into 0x20000000- * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. */ phys_to_dma_offset = 0x10000000; break; default: phys_to_dma_offset = 0x00000000; break; } }
void __init configure_platform(void) { platform_set_family(); switch (platform_family) { case FAMILY_1500: case FAMILY_1500VZE: case FAMILY_1500VZF: platform_features = FFS_CAPABLE; asic = ASIC_CALLIOPE; set_register_map(CALLIOPE_IO_BASE, &calliope_register_map); if (platform_family == FAMILY_1500VZE) { gp_resources = non_dvr_vze_calliope_resources; pr_info("Platform: 1500/Vz Class E - " "CALLIOPE, NON_DVR_CAPABLE\n"); } else if (platform_family == FAMILY_1500VZF) { gp_resources = non_dvr_vzf_calliope_resources; pr_info("Platform: 1500/Vz Class F - " "CALLIOPE, NON_DVR_CAPABLE\n"); } else { gp_resources = non_dvr_calliope_resources; pr_info("Platform: 1500/RNG100 - CALLIOPE, " "NON_DVR_CAPABLE\n"); } break; case FAMILY_4500: platform_features = FFS_CAPABLE | PCIE_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_ZEUS; set_register_map(ZEUS_IO_BASE, &zeus_register_map); gp_resources = non_dvr_zeus_resources; pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); break; case FAMILY_4600: { unsigned int chipversion = 0; platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; set_register_map(CRONUS_IO_BASE, &cronus_register_map); chipversion = asic_read(chipver3) << 24; chipversion |= asic_read(chipver2) << 16; chipversion |= asic_read(chipver1) << 8; chipversion |= asic_read(chipver0); if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) asic = ASIC_CRONUS; else asic = ASIC_CRONUSLITE; gp_resources = non_dvr_cronuslite_resources; pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " "chipversion=0x%08X\n", (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", chipversion); break; } case FAMILY_4600VZA: platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_CRONUS; set_register_map(CRONUS_IO_BASE, &cronus_register_map); gp_resources = non_dvr_cronus_resources; pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); break; case FAMILY_8500: case FAMILY_8500RNG: platform_features = DVR_CAPABLE | PCIE_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_ZEUS; set_register_map(ZEUS_IO_BASE, &zeus_register_map); gp_resources = dvr_zeus_resources; pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n"); break; case FAMILY_8600: case FAMILY_8600VZB: platform_features = DVR_CAPABLE | PCIE_CAPABLE | DISPLAY_CAPABLE; asic = ASIC_CRONUS; set_register_map(CRONUS_IO_BASE, &cronus_register_map); gp_resources = dvr_cronus_resources; pr_info("Platform: 8600/Vz Class B - CRONUS, " "DVR_CAPABLE\n"); break; case FAMILY_8700: platform_features = FFS_CAPABLE | PCIE_CAPABLE; asic = ASIC_GAIA; set_register_map(GAIA_IO_BASE, &gaia_register_map); gp_resources = dvr_gaia_resources; pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n"); break; default: pr_crit("Platform: UNKNOWN PLATFORM\n"); break; } switch (asic) { case ASIC_ZEUS: phys_to_dma_offset = 0x30000000; break; case ASIC_CALLIOPE: phys_to_dma_offset = 0x10000000; break; case ASIC_CRONUSLITE: case ASIC_CRONUS: phys_to_dma_offset = 0x10000000; break; default: phys_to_dma_offset = 0x00000000; break; } }
/* * \brief usb_eye_configure() for optimizing the USB eye on Calliope. * * \param unsigned int value saved to the register. * * \return none * */ static void __init usb_eye_configure(unsigned int value) { asic_write(asic_read(crt_spare) | value, crt_spare); }