status_code_t nvm_init(mem_type_t mem)
{
switch (mem) {
case INT_FLASH:
#if SAM4S
case INT_USERPAGE:
#endif
break;
#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
case AT45DBX:
/* Initialize dataflash */
at45dbx_init();
/* Perform memory check */
if (!at45dbx_mem_check()) {
return ERR_NO_MEMORY;
}
break;
#endif
default:
return ERR_INVALID_ARG;
}
return STATUS_OK;
}
/*! \brief Main function. Execution starts here.
*/
int main(void)
{
//Initialize interrupt controller
irq_initialize_vectors();
cpu_irq_enable();
// Initialize sleep manager
sleepmgr_init();
// Initialize clock tree
sysclk_init();
// Initialize hardware board resources
board_init();
// Initialize user interface
ui_init();
ui_powerdown();
// Sanity check about Silicon revision Vs Firmware build
// for Silicon revision A, firmware should be specific
if ((!firmware_rev_a) && (nvm_read_device_rev()==0)) {
ui_si_revision_error();
while(ui_button()!=1);
while(ui_button()!=2);
while(ui_button()!=4);
while(ui_button()!=8);
}
// Initialize DATA Flash
at45dbx_init();
// Initialize ADC for on-board sensors
adc_sensors_init();
// Initialize USB HID report protocol
usb_hid_com_init();
// Start USB stack
main_build_usb_serial_number();
udc_start();
// The main loop manages only the power mode
// because everything else is managed by interrupt.
// The USB Start of Frame event manages internal tick events for
// on-board sensor updates as well as LCD display update.
while (true) {
if (main_b_msc_enable) {
if (!udi_msc_process_trans()) {
sleepmgr_enter_sleep();
}
} else {
sleepmgr_enter_sleep();
}
if (usb_hid_com_is_start_dfu()) {
main_start_dfu_session();
}
}
}
void memories_initialization(void)
{
#if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE)
// sysclk_enable_peripheral_clock(AT45DBX_SPI_MODULE);
// is already done by XMEGA SPI driver
at45dbx_init();
#endif
}
void memories_initialization(void)
{
#ifdef CONF_BOARD_AT45DBX
at45dbx_init();
if (at45dbx_mem_check() != true) {
while (1) {
}
}
#endif
}
/**
* \brief Run DataFlash component unit tests
*
* Initializes the clock system, board, serial output and DataFlash, then sets
* up the DataFlash unit test suite and runs it.
*/
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS,
};
// Initialize the board and all the peripheral required
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
at45dbx_init();
// Define all the test cases
DEFINE_TEST_CASE(memory_check_test, NULL, run_memory_check_test, NULL,
"Memory check");
DEFINE_TEST_CASE(byte_access_test, NULL, run_byte_access_test, NULL,
"Read/write byte access");
DEFINE_TEST_CASE(sector_access_test, NULL, run_sector_access_test, NULL,
"Read/write sector access");
DEFINE_TEST_CASE(multiple_sector_access_test, NULL,
run_multiple_sector_access_test, NULL,
"Read/write multiple sector access");
DEFINE_TEST_CASE(memory_range_check_test, NULL,
run_memory_range_check_test, NULL,
"Memory range address check");
// Put test case addresses in an array.
DEFINE_TEST_ARRAY(memory_tests) = {
&memory_check_test,
&byte_access_test,
§or_access_test,
&multiple_sector_access_test,
&memory_range_check_test
};
// Define the test suite.
DEFINE_TEST_SUITE(memory_suite, memory_tests,
"AT45dbx component unit test suite");
// Run all tests in the test suite.
test_suite_run(&memory_suite);
while (1) {
// Intentionally left empty.
};
}
/*! \brief Main function. Execution starts here.
*/
int main(void)
{
irq_initialize_vectors();
cpu_irq_enable();
// Initialize the sleep manager
sleepmgr_init();
sysclk_init();
board_init();
ui_init();
ui_powerdown();
#if UC3A3
// Init Hmatrix bus
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
init_hmatrix();
#endif
#if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE)
at45dbx_init();
#endif
#if ((defined SD_MMC_MCI_0_MEM) && (SD_MMC_MCI_0_MEM == ENABLE)) \
|| ((defined SD_MMC_MCI_1_MEM) && (SD_MMC_MCI_1_MEM == ENABLE))
// Initialize SD/MMC with MCI PB clock.
sysclk_enable_pbb_module(SYSCLK_MCI);
sysclk_enable_hsb_module(SYSCLK_DMACA);
sd_mmc_mci_resources_init();
#endif
// Start USB stack to authorize VBus monitoring
udc_start();
if (!udc_include_vbus_monitoring()) {
// VBUS monitoring is not available on this product
// thereby VBUS has to be considered as present
main_vbus_action(true);
}
// The main loop manages only the power mode
// because the USB management is done by interrupt
while (true) {
sleepmgr_enter_sleep();
if (main_b_msc_enable) {
udi_msc_process_trans();
}
}
}
void memories_initialization(void)
{
#ifdef CONF_BOARD_SMC_PSRAM
psram_init();
#endif
#ifdef CONF_BOARD_SRAM
sram_init();
#endif
#ifdef CONF_BOARD_SDRAMC
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SMC);
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&SDRAM_MICRON_MT48LC16M16A2,
sysclk_get_cpu_hz());
#endif
#ifdef CONF_BOARD_AT45DBX
at45dbx_init();
if (at45dbx_mem_check() != true) {
while (1) {
}
}
#endif
#ifdef CONF_BOARD_SD_MMC_HSMCI
uint8_t slot = 0;
sd_mmc_err_t err;
sd_mmc_init();
if (slot == sd_mmc_nb_slot()) {
slot = 0;
}
// Wait for a card and ready
do {
err = sd_mmc_check(slot);
if ((SD_MMC_ERR_NO_CARD != err)
&& (SD_MMC_INIT_ONGOING != err)
&& (SD_MMC_OK != err)) {
while (SD_MMC_ERR_NO_CARD != sd_mmc_check(slot)) {
}
}
} while (SD_MMC_OK != err);
#endif
}
/*! \brief Main function.
*/
int main(void)
{
uint16_t i;
// Initialize the system - clock and board.
system_init();
at45dbx_init();
if(at45dbx_mem_check()==true) {
port_pin_set_output_level(DATA_FLASH_LED_EXAMPLE_0, false);
} else
{
test_ko();
}
// Prepare half a data flash sector to 0xAA
for(i=0;i<AT45DBX_SECTOR_SIZE/2;i++) {
ram_buf[i]=0xAA;
}
// And the remaining half to 0x55
for(;i<AT45DBX_SECTOR_SIZE;i++) {
ram_buf[i]=0x55;
}
at45dbx_write_sector_open(TARGET_SECTOR);
at45dbx_write_sector_from_ram(ram_buf);
at45dbx_write_close();
// Read back this sector and compare to expected values
at45dbx_read_sector_open(TARGET_SECTOR);
at45dbx_read_sector_to_ram(ram_buf);
at45dbx_read_close();
for(i=0;i<AT45DBX_SECTOR_SIZE/2;i++) {
if (ram_buf[i]!=0xAA) {
test_ko();
}
}
for(;i<AT45DBX_SECTOR_SIZE;i++) {
if (ram_buf[i]!=0x55) {
test_ko();
}
}
// Write one data flash sector to 0x00, 0x01 ....
for(i=0;i<AT45DBX_SECTOR_SIZE;i++) {
ram_buf[i]=i;
}
at45dbx_write_sector_open(TARGET_SECTOR);
at45dbx_write_sector_from_ram(ram_buf);
at45dbx_write_close();
// Read one data flash sector to ram
at45dbx_read_sector_open(TARGET_SECTOR);
at45dbx_read_sector_to_ram(ram_buf);
at45dbx_read_close();
for(i=0;i<AT45DBX_SECTOR_SIZE;i++) {
if ( ram_buf[i]!=(i%0x100) ) {
test_ko();
}
}
while (1);
}
void memories_initialization(void)
{
//-- Hmatrix bus configuration
// This improve speed performance
#ifdef AVR32_HMATRIXB
union {
unsigned long scfg;
avr32_hmatrixb_scfg_t SCFG;
} u_avr32_hmatrixb_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH] =
u_avr32_hmatrixb_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM] =
u_avr32_hmatrixb_scfg.scfg;
# ifdef AVR32_HMATRIXB_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI] =
u_avr32_hmatrixb_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX
union {
unsigned long scfg;
avr32_hmatrix_scfg_t SCFG;
} u_avr32_hmatrix_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] =
u_avr32_hmatrix_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] =
u_avr32_hmatrix_scfg.scfg;
# ifdef AVR32_HMATRIX_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI] =
u_avr32_hmatrix_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX_MASTER_USBB_DMA
union {
unsigned long mcfg;
avr32_hmatrix_mcfg_t MCFG;
} u_avr32_hmatrix_mcfg;
// For the USBB DMA HMATRIX master, use infinite length burst.
u_avr32_hmatrix_mcfg.mcfg =
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA];
u_avr32_hmatrix_mcfg.MCFG.ulbt =
AVR32_HMATRIX_ULBT_INFINITE;
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA] =
u_avr32_hmatrix_mcfg.mcfg;
// For the USBB DPRAM HMATRIX slave, use the USBB DMA as fixed default master.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM];
u_avr32_hmatrix_scfg.SCFG.fixed_defmstr =
AVR32_HMATRIX_MASTER_USBB_DMA;
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM] =
u_avr32_hmatrix_scfg.scfg;
#endif
#if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE)
at45dbx_init();
#endif
#if ((defined SD_MMC_0_MEM) && (SD_MMC_0_MEM == ENABLE)) \
|| ((defined SD_MMC_1_MEM) && (SD_MMC_1_MEM == ENABLE))
sd_mmc_init();
#endif
}
/*! \brief Sets up USART for shell.
*
* \param pba_hz The current module frequency.
*/
static void init_shl_rs232(long pba_hz)
{
// GPIO map for USART.
static const gpio_map_t SHL_USART_GPIO_MAP =
{
{SHL_USART_RX_PIN, SHL_USART_RX_FUNCTION},
{SHL_USART_TX_PIN, SHL_USART_TX_FUNCTION}
};
// Options for USART.
static const usart_options_t SHL_USART_OPTIONS =
{
.baudrate = SHL_USART_BAUDRATE,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = USART_NORMAL_CHMODE
};
// Set up GPIO for SHL_USART, size of the GPIO map is 2 here.
gpio_enable_module(SHL_USART_GPIO_MAP,
sizeof(SHL_USART_GPIO_MAP) / sizeof(SHL_USART_GPIO_MAP[0]));
// Initialize it in RS232 mode.
usart_init_rs232(SHL_USART, &SHL_USART_OPTIONS, pba_hz);
}
/*! \brief Initializes the dataflash memory AT45DBX resources: GPIO, SPI and AT45DBX.
*/
static void at45dbx_resources_init(void)
{
// GPIO map for SPI.
static const gpio_map_t AT45DBX_SPI_GPIO_MAP =
{
{AT45DBX_SPI_SCK_PIN, AT45DBX_SPI_SCK_FUNCTION }, // SPI Clock.
{AT45DBX_SPI_MISO_PIN, AT45DBX_SPI_MISO_FUNCTION }, // MISO.
{AT45DBX_SPI_MOSI_PIN, AT45DBX_SPI_MOSI_FUNCTION }, // MOSI.
#define AT45DBX_ENABLE_NPCS_PIN(NPCS, unused) \
{AT45DBX_SPI_NPCS##NPCS##_PIN, AT45DBX_SPI_NPCS##NPCS##_FUNCTION}, // Chip Select NPCS.
MREPEAT(AT45DBX_MEM_CNT, AT45DBX_ENABLE_NPCS_PIN, ~)
#undef AT45DBX_ENABLE_NPCS_PIN
};
// Options for SPI.
spi_options_t spiOptions =
{
.reg = AT45DBX_SPI_FIRST_NPCS, // Defined in conf_at45dbx.h.
.baudrate = AT45DBX_SPI_MASTER_SPEED, // Defined in conf_at45dbx.h.
.bits = AT45DBX_SPI_BITS, // Defined in conf_at45dbx.h.
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 1,
.spi_mode = 0,
.modfdis = 1
};
// Assign I/Os to SPI.
gpio_enable_module(AT45DBX_SPI_GPIO_MAP,
sizeof(AT45DBX_SPI_GPIO_MAP) / sizeof(AT45DBX_SPI_GPIO_MAP[0]));
// Initialize as master.
spi_initMaster(AT45DBX_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay.
spi_selectionMode(AT45DBX_SPI, 0, 0, 0);
// Enable SPI.
spi_enable(AT45DBX_SPI);
// Initialize data flash with SPI clock Osc0.
at45dbx_init(spiOptions, FOSC0);
}
/*! \brief Main function. Execution starts here.
*/
int main(void)
{
U8 i, j;
U16 file_size;
Fs_index sav_index;
static Fs_index mark_index;
const char *part_type;
U32 VarTemp;
// Switch to external oscillator 0.
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
// Initialize RS232 shell text output.
init_shl_rs232(FOSC0);
// Initialize AT45DBX resources: GPIO, SPI and AT45DBX.
at45dbx_resources_init();
// Display memory status
print(SHL_USART, MSG_WELCOME "\nMemory ");
// Test if the memory is ready - using the control access memory abstraction layer (/SERVICES/MEMORY/CTRL_ACCESS/)
if (mem_test_unit_ready(LUN_ID_AT45DBX_MEM) == CTRL_GOOD)
{
// Get and display the capacity
mem_read_capacity(LUN_ID_AT45DBX_MEM, &VarTemp);
print(SHL_USART, "OK:\t");
print_ulong(SHL_USART, (VarTemp + 1) >> (20 - FS_SHIFT_B_TO_SECTOR));
print(SHL_USART, " MB\n");
}
/*! \brief Main function.
*/
int main(void)
{
uint16_t i;
sysclk_init();
// Initialize the board.
// The board-specific conf_board.h file contains the configuration of the board
// initialization.
board_init();
at45dbx_init();
if(at45dbx_mem_check()==true) {
gpio_set_pin_low(DATA_FLASH_LED_EXAMPLE_0);
} else
{
test_ko();
}
// Prepare half a data flash sector to 0xAA
for(i=0;i<AT45DBX_SECTOR_SIZE/2;i++) {
ram_buf[i]=0xAA;
}
// And the remaining half to 0x55
for(;i<AT45DBX_SECTOR_SIZE;i++) {
ram_buf[i]=0x55;
}
at45dbx_write_sector_open(TARGET_SECTOR);
at45dbx_write_sector_from_ram(ram_buf);
at45dbx_write_close();
// Read back this sector and compare to expected values
at45dbx_read_sector_open(TARGET_SECTOR);
at45dbx_read_sector_to_ram(ram_buf);
at45dbx_read_close();
for(i=0;i<AT45DBX_SECTOR_SIZE/2;i++) {
if (ram_buf[i]!=0xAA) {
test_ko();
}
}
for(;i<AT45DBX_SECTOR_SIZE;i++) {
if (ram_buf[i]!=0x55) {
test_ko();
}
}
// Write one data flash sector to 0x00, 0x01 ....
for(i=0;i<AT45DBX_SECTOR_SIZE;i++) {
ram_buf[i]=i;
}
at45dbx_write_sector_open(TARGET_SECTOR);
at45dbx_write_sector_from_ram(ram_buf);
at45dbx_write_close();
// Read one data flash sector to ram
at45dbx_read_sector_open(TARGET_SECTOR);
at45dbx_read_sector_to_ram(ram_buf);
at45dbx_read_close();
for(i=0;i<AT45DBX_SECTOR_SIZE;i++) {
if ( ram_buf[i]!=(i%0x100) ) {
test_ko();
}
}
gpio_set_pin_low(DATA_FLASH_LED_EXAMPLE_1);
while (1);
}
void memories_initialization(void)
{
at45dbx_init();
}
void memories_initialization(void)
{
//-- Hmatrix bus configuration
// This improve speed performance
#ifdef AVR32_HMATRIXB
union {
unsigned long scfg;
avr32_hmatrixb_scfg_t SCFG;
} u_avr32_hmatrixb_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH] =
u_avr32_hmatrixb_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM] =
u_avr32_hmatrixb_scfg.scfg;
# ifdef AVR32_HMATRIXB_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI] =
u_avr32_hmatrixb_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX
union {
unsigned long scfg;
avr32_hmatrix_scfg_t SCFG;
} u_avr32_hmatrix_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] =
u_avr32_hmatrix_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] =
u_avr32_hmatrix_scfg.scfg;
# ifdef AVR32_HMATRIX_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI] =
u_avr32_hmatrix_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX_MASTER_USBB_DMA
union {
unsigned long mcfg;
avr32_hmatrix_mcfg_t MCFG;
} u_avr32_hmatrix_mcfg;
// For the USBB DMA HMATRIX master, use infinite length burst.
u_avr32_hmatrix_mcfg.mcfg =
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA];
u_avr32_hmatrix_mcfg.MCFG.ulbt =
AVR32_HMATRIX_ULBT_INFINITE;
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA] =
u_avr32_hmatrix_mcfg.mcfg;
// For the USBB DPRAM HMATRIX slave, use the USBB DMA as fixed default master.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM];
u_avr32_hmatrix_scfg.SCFG.fixed_defmstr =
AVR32_HMATRIX_MASTER_USBB_DMA;
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM] =
u_avr32_hmatrix_scfg.scfg;
#endif
#if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE)
sysclk_enable_peripheral_clock(AT45DBX_SPI_MODULE);
at45dbx_init();
#endif
#if ((defined SD_MMC_MCI_0_MEM) && (SD_MMC_MCI_0_MEM == ENABLE)) \
|| ((defined SD_MMC_MCI_1_MEM) && (SD_MMC_MCI_1_MEM == ENABLE))
sysclk_enable_pbb_module(SYSCLK_MCI);
sysclk_enable_hsb_module(SYSCLK_DMACA);
sd_mmc_mci_init(SD_SLOT_8BITS, sysclk_get_pbb_hz(), sysclk_get_cpu_hz());
#endif
#if (defined SD_MMC_SPI_MEM) && (SD_MMC_SPI_MEM == ENABLE)
// SPI options.
spi_options_t spiOptions = {
.reg = SD_MMC_SPI_NPCS,
.baudrate = SD_MMC_SPI_MASTER_SPEED, // Defined in conf_sd_mmc_spi.h.
.bits = SD_MMC_SPI_BITS, // Defined in conf_sd_mmc_spi.h.
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 1,
.spi_mode = 0,
.modfdis = 1
};
sysclk_enable_peripheral_clock(SD_MMC_SPI);
// If the SPI used by the SD/MMC is not enabled.
if (!spi_is_enabled(SD_MMC_SPI)) {
// Initialize as master.
spi_initMaster(SD_MMC_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay.
spi_selectionMode(SD_MMC_SPI, 0, 0, 0);
// Enable SPI.
spi_enable(SD_MMC_SPI);
}
// Initialize SD/MMC with SPI PB clock.
sd_mmc_spi_init(spiOptions,sysclk_get_pba_hz());
#endif // SD_MMC_SPI_MEM == ENABLE
}