static void __init dir825b1_wlan_init(void)
{
u8 *caldata;
u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN];
caldata = (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0);
if (!dir825b1_is_caldata_valid(caldata)) {
caldata = (u8 *)KSEG1ADDR(DIR825B1_CAL_LOCATION_1);
if (!dir825b1_is_caldata_valid(caldata)) {
pr_err("no calibration data found\n");
return;
}
}
ath79_parse_ascii_mac(caldata + DIR825B1_MAC0_OFFSET, mac0);
ath79_parse_ascii_mac(caldata + DIR825B1_MAC1_OFFSET, mac1);
ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0);
ath79_init_mac(wmac0, mac0, 0);
ath79_init_mac(wmac1, mac1, 1);
ap9x_pci_setup_wmac_led_pin(0, 5);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap94_pci_init(caldata + DIR825B1_CAL0_OFFSET, wmac0,
caldata + DIR825B1_CAL1_OFFSET, wmac1);
}
static void __init tew673gru_wlan_init(void)
{
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
u8 *caldata;
caldata = (u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_0);
if (!tew673gru_is_caldata_valid(caldata)) {
caldata = (u8 *)KSEG1ADDR(TEW673GRU_CAL_LOCATION_1);
if (!tew673gru_is_caldata_valid(caldata)) {
pr_err("no calibration data found\n");
return;
}
}
ath79_parse_ascii_mac(caldata + TEW673GRU_MAC0_OFFSET, mac1);
ath79_parse_ascii_mac(caldata + TEW673GRU_MAC1_OFFSET, mac2);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
ap9x_pci_setup_wmac_led_pin(0, 5);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap94_pci_init(caldata + TEW673GRU_CAL0_OFFSET, mac1,
caldata + TEW673GRU_CAL1_OFFSET, mac2);
}
static void __init tew_732br_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(TEW_732BR_ART_ADDRESS);
u8 lan_mac[ETH_ALEN];
u8 wan_mac[ETH_ALEN];
ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_732br_leds_gpio),
tew_732br_leds_gpio);
ath79_register_gpio_keys_polled(1, TEW_732BR_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tew_732br_gpio_keys),
tew_732br_gpio_keys);
ath79_register_m25p80(NULL);
ath79_parse_ascii_mac(art + TEW_732BR_LAN_MAC_OFFSET, lan_mac);
ath79_parse_ascii_mac(art + TEW_732BR_WAN_MAC_OFFSET, wan_mac);
ath79_register_wmac(art + TEW_732BR_CALDATA_OFFSET, lan_mac);
ath79_register_mdio(1, 0x0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
/* LAN: GMAC1 is connected to the internal switch */
ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN: GMAC0 is connected to the PHY4 of the internal switch */
ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
}
static void __init dir825c1_generic_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN];
ath79_parse_ascii_mac(mac + DIR825C1_MAC0_OFFSET, mac0);
ath79_parse_ascii_mac(mac + DIR825C1_MAC1_OFFSET, mac1);
ath79_register_m25p80(NULL);
ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825c1_gpio_keys),
dir825c1_gpio_keys);
ath79_init_mac(wmac0, mac0, 0);
ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, wmac0);
ath79_init_mac(wmac1, mac1, 1);
ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, wmac1);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(dir825c1_mdio0_info,
ARRAY_SIZE(dir825c1_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init tew_712br_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(TEW_712BR_ART_ADDRESS);
u8 *mac = (u8 *) KSEG1ADDR(TEW_712BR_MAC_PART_ADDRESS);
u8 lan_mac[ETH_ALEN];
u8 wan_mac[ETH_ALEN];
ath79_setup_ar933x_phy4_switch(false, false);
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
gpio_request_one(TEW_712BR_GPIO_WAN_LED_ENABLE,
GPIOF_OUT_INIT_LOW, "WAN LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_712br_leds_gpio),
tew_712br_leds_gpio);
ath79_register_gpio_keys_polled(1, TEW_712BR_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tew_712br_gpio_keys),
tew_712br_gpio_keys);
ath79_register_m25p80(NULL);
ath79_parse_ascii_mac(mac + TEW_712BR_LAN_MAC_OFFSET, lan_mac);
ath79_parse_ascii_mac(mac + TEW_712BR_WAN_MAC_OFFSET, wan_mac);
ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_eth(0);
ath79_register_wmac(art + TEW_712BR_CALDATA_OFFSET, wan_mac);
}
