/** * Misc invariant state packets */ void brw_upload_invariant_state(struct brw_context *brw) { const bool is_965 = brw->gen == 4 && !brw->is_g4x; brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); brw->last_pipeline = BRW_RENDER_PIPELINE; if (brw->gen >= 8) { BEGIN_BATCH(3); OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } else { BEGIN_BATCH(2); OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2)); OUT_BATCH(0); ADVANCE_BATCH(); } const uint32_t _3DSTATE_VF_STATISTICS = is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS; BEGIN_BATCH(1); OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 | 1); ADVANCE_BATCH(); }
/** * Misc invariant state packets */ void brw_upload_invariant_state(struct brw_context *brw) { const bool is_965 = brw->gen == 4 && !brw->is_g4x; brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); brw->last_pipeline = BRW_RENDER_PIPELINE; if (brw->gen >= 8) { BEGIN_BATCH(3); OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } else { BEGIN_BATCH(2); OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2)); OUT_BATCH(0); ADVANCE_BATCH(); } /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */ if (!is_965) { BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2)); /* use legacy aa line coverage computation */ OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } const uint32_t _3DSTATE_VF_STATISTICS = is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS; BEGIN_BATCH(1); OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 | 1); ADVANCE_BATCH(); }