/* Requirements : HL_SR408 */
void tms570_check_tcram_ecc( void )
{
volatile uint64_t ramread;
volatile uint32_t regread;
uint32_t tcram1ErrStat, tcram2ErrStat = 0U;
uint64_t tcramA1_bk = tcramA1bit;
uint64_t tcramB1_bk = tcramB1bit;
uint64_t tcramA2_bk = tcramA2bit;
uint64_t tcramB2_bk = tcramB2bit;
/* Clear RAMOCUUR before setting RAMTHRESHOLD register */
TMS570_TCRAM1.RAMOCCUR = 0U;
TMS570_TCRAM2.RAMOCCUR = 0U;
/* Set Single-bit Error Threshold Count as 1 */
TMS570_TCRAM1.RAMTHRESHOLD = 1U;
TMS570_TCRAM2.RAMTHRESHOLD = 1U;
/* Enable single bit error generation */
TMS570_TCRAM1.RAMINTCTRL = 1U;
TMS570_TCRAM2.RAMINTCTRL = 1U;
/* Enable writes to ECC RAM, enable ECC error response */
TMS570_TCRAM1.RAMCTRL = 0x0005010AU;
TMS570_TCRAM2.RAMCTRL = 0x0005010AU;
/* Force a single bit error in both the banks */
_coreDisableRamEcc_();
tcramA1bitError ^= 1U;
tcramB1bitError ^= 1U;
_coreEnableRamEcc_();
/* Read the corrupted data to generate single bit error */
ramread = tcramA1bit;
ramread = tcramB1bit;
(void)ramread;
/* Check for error status */
tcram1ErrStat = TMS570_TCRAM1.RAMERRSTATUS & 0x1U;
tcram2ErrStat = TMS570_TCRAM2.RAMERRSTATUS & 0x1U;
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */
if ((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) {
/* TCRAM module does not reflect 1-bit error reported by CPU */
bsp_selftest_fail_notification(CHECKRAMECC_FAIL1);
} else {
if (!tms570_esm_channel_sr_get(1, 26) || !tms570_esm_channel_sr_get(1, 28)) {
/* TCRAM 1-bit error not flagged in ESM */
bsp_selftest_fail_notification(CHECKRAMECC_FAIL2);
} else {
/* Clear single bit error flag in TCRAM module */
TMS570_TCRAM1.RAMERRSTATUS = 0x1U;
TMS570_TCRAM2.RAMERRSTATUS = 0x1U;
/* Clear ESM status */
tms570_esm_channel_sr_clear(1, 26);
tms570_esm_channel_sr_clear(1, 28);
}
}
#if 0
/*
* This test sequence requires that data abort exception
* handler checks for ECC test write enable in RAMCTR (bit 8)
* and if the access abort is intended then it should clear
* error status TCRAM status register and checks and clears
* ESM group3 uncorrectable TCRAM error channels.
*
* More modifications in BSP and RTEMS ARM support are
* required to make this code work.
*/
/* Force a double bit error in both the banks */
_coreDisableRamEcc_();
tcramA2bitError ^= 3U;
tcramB2bitError ^= 3U;
_coreEnableRamEcc_();
/* Read the corrupted data to generate double bit error */
ramread = tcramA2bit;
ramread = tcramB2bit;
/* read from location with 2-bit ECC error this will cause a data abort to be generated */
/* See HalCoGen support src/sys/asm/dabort.asm */
/* _ARMV4_Exception_data_abort_default has to include solution for this special case for RTEMS */
#endif
regread = TMS570_TCRAM1.RAMUERRADDR;
regread = TMS570_TCRAM2.RAMUERRADDR;
(void)regread;
/* disable writes to ECC RAM */
TMS570_TCRAM1.RAMCTRL = 0x0005000AU;
TMS570_TCRAM2.RAMCTRL = 0x0005000AU;
/* Compute correct ECC */
tcramA1bit = tcramA1_bk;
tcramB1bit = tcramB1_bk;
tcramA2bit = tcramA2_bk;
tcramB2bit = tcramB2_bk;
}
/* Requirements : HL_SR471 */
void tms570_system_hw_init( void )
{
uint32_t efc_check_status;
/* Configure PLL control registers and enable PLLs.
* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
* This initialization sequence performs all the tasks that are not
* required to be done at full application speed while the PLL locks.
*/
tms570_pll_init();
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efc_check_status = tms570_efc_check();
/* Enable clocks to peripherals and release peripheral reset */
tms570_periph_init();
/* Configure device-level multiplexing and I/O multiplexing */
tms570_pinmux_init();
/* Enable external memory interface */
TMS570_SYS1.GPREG1 |= TMS570_SYS1_GPREG1_EMIF_FUNC;
if ( efc_check_status == 0U ) {
/* Wait for eFuse controller self-test to complete and check results */
if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); /* device operation is not reliable */
}
} else if ( efc_check_status == 2U ) {
/* Wait for eFuse controller self-test to complete and check results */
if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); /* device operation is not reliable */
} else {
bsp_selftest_fail_notification( EFCCHECK_FAIL2 );
}
} else {
/* Empty */
}
/** - Set up flash address and data wait states based on the target CPU clock frequency
* The number of address and data wait states for the target CPU clock frequency are specified
* in the specific part's datasheet.
*/
tms570_flash_init();
/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
tms570_trim_lpo_init();
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
tms570_map_clock_init();
/** - set ECLK pins functional mode */
TMS570_SYS1.SYSPC1 = 0U;
/** - set ECLK pins default output value */
TMS570_SYS1.SYSPC4 = 0U;
/** - set ECLK pins output direction */
TMS570_SYS1.SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
TMS570_SYS1.SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
TMS570_SYS1.SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
TMS570_SYS1.SYSPC9 = 1U;
/** - Setup ECLK */
TMS570_SYS1.ECPCNTL = TMS570_SYS1_ECPCNTL_ECPSSEL * 0 |
TMS570_SYS1_ECPCNTL_ECPCOS * 0 |
TMS570_SYS1_ECPCNTL_ECPDIV( 8 - 1 );
}
