static int ata_pccard_probe(device_t dev) { struct ata_channel *ch = device_get_softc(dev); struct resource *io; int rid, len, start, end; u_long tmp; /* allocate the io range to get start and length */ rid = ATA_IOADDR_RID; len = bus_get_resource_count(dev, SYS_RES_IOPORT, rid); io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, ATA_IOSIZE, RF_ACTIVE); if (!io) return ENOMEM; /* reallocate the io address to only cover the io ports */ start = rman_get_start(io); end = start + ATA_IOSIZE - 1; bus_release_resource(dev, SYS_RES_IOPORT, rid, io); io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, start, end, ATA_IOSIZE, RF_ACTIVE); bus_release_resource(dev, SYS_RES_IOPORT, rid, io); /* * if we got more than the default ATA_IOSIZE ports, this is likely * a pccard system where the altio ports are located at offset 14 * otherwise its the normal altio offset */ if (bus_get_resource(dev, SYS_RES_IOPORT, ATA_ALTADDR_RID, &tmp, &tmp)) { if (len > ATA_IOSIZE) { bus_set_resource(dev, SYS_RES_IOPORT, ATA_ALTADDR_RID, start + ATA_PCCARD_ALTOFFSET, ATA_ALTIOSIZE); } else { bus_set_resource(dev, SYS_RES_IOPORT, ATA_ALTADDR_RID, start + ATA_ALTOFFSET, ATA_ALTIOSIZE); } } else return ENOMEM; ch->unit = 0; ch->flags |= (ATA_USE_16BIT | ATA_NO_SLAVE); return ata_probe(dev); }
static int ed_pccard_attach(device_t dev) { u_char sum; u_char enaddr[ETHER_ADDR_LEN]; const struct ed_product *pp; int error, i, flags, port_rid, modem_rid; struct ed_softc *sc = device_get_softc(dev); u_long size; static uint16_t *intr_vals[] = {NULL, NULL}; sc->dev = dev; if ((pp = (const struct ed_product *) pccard_product_lookup(dev, (const struct pccard_product *) ed_pccard_products, sizeof(ed_pccard_products[0]), NULL)) == NULL) { printf("Can't find\n"); return (ENXIO); } modem_rid = port_rid = -1; if (pp->flags & NE2000DVF_MODEM) { for (i = 0; i < 4; i++) { size = bus_get_resource_count(dev, SYS_RES_IOPORT, i); if (size == ED_NOVELL_IO_PORTS) port_rid = i; else if (size == 8) modem_rid = i; } if (port_rid == -1) { device_printf(dev, "Cannot locate my ports!\n"); return (ENXIO); } } else { port_rid = 0; } /* Allocate the port resource during setup. */ error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); if (error) { printf("alloc_port failed\n"); return (error); } if (rman_get_size(sc->port_res) == ED_NOVELL_IO_PORTS / 2) { port_rid++; sc->port_res2 = bus_alloc_resource(dev, SYS_RES_IOPORT, &port_rid, 0ul, ~0ul, 1, RF_ACTIVE); if (sc->port_res2 == NULL || rman_get_size(sc->port_res2) != ED_NOVELL_IO_PORTS / 2) { error = ENXIO; goto bad; } } error = ed_alloc_irq(dev, 0, 0); if (error) goto bad; /* * Determine which chipset we are. Almost all the PC Card chipsets * have the Novel ASIC and NIC offsets. There's 2 known cards that * follow the WD80x3 conventions, which are handled as a special case. */ sc->asic_offset = ED_NOVELL_ASIC_OFFSET; sc->nic_offset = ED_NOVELL_NIC_OFFSET; error = ENXIO; flags = device_get_flags(dev); if (error != 0) error = ed_pccard_dl100xx(dev, pp); if (error != 0) error = ed_pccard_ax88x90(dev, pp); if (error != 0) error = ed_pccard_tc5299j(dev, pp); if (error != 0) { error = ed_probe_Novell_generic(dev, flags); printf("Novell generic probe failed: %d\n", error); } if (error != 0 && (pp->flags & NE2000DVF_TOSHIBA)) { flags |= ED_FLAGS_TOSH_ETHER; flags |= ED_FLAGS_PCCARD; sc->asic_offset = ED_WD_ASIC_OFFSET; sc->nic_offset = ED_WD_NIC_OFFSET; error = ed_probe_WD80x3_generic(dev, flags, intr_vals); } if (error) goto bad; /* * There are several ways to get the MAC address for the card. * Some of the above probe routines can fill in the enaddr. If * not, we run through a number of 'well known' locations: * (1) From the PC Card FUNCE * (2) From offset 0 in the shared memory * (3) From a hinted offset in attribute memory * (4) From 0xff0 in attribute memory * If we can't get a non-zero MAC address from this list, we fail. */ for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) sum |= sc->enaddr[i]; if (sum == 0) { pccard_get_ether(dev, enaddr); if (bootverbose) device_printf(dev, "CIS MAC %6D\n", enaddr, ":"); for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) sum |= enaddr[i]; if (sum == 0 && ed_pccard_rom_mac(dev, enaddr)) { if (bootverbose) device_printf(dev, "ROM mac %6D\n", enaddr, ":"); sum++; } if (sum == 0 && pp->flags & NE2000DVF_ENADDR) { for (i = 0; i < ETHER_ADDR_LEN; i++) { pccard_attr_read_1(dev, pp->enoff + i * 2, enaddr + i); sum |= enaddr[i]; } if (bootverbose) device_printf(dev, "Hint %x MAC %6D\n", pp->enoff, enaddr, ":"); } if (sum == 0) { for (i = 0; i < ETHER_ADDR_LEN; i++) { pccard_attr_read_1(dev, ED_DEFAULT_MAC_OFFSET + i * 2, enaddr + i); sum |= enaddr[i]; } if (bootverbose) device_printf(dev, "Fallback MAC %6D\n", enaddr, ":"); } if (sum == 0) { device_printf(dev, "Cannot extract MAC address.\n"); ed_release_resources(dev); return (ENXIO); } bcopy(enaddr, sc->enaddr, ETHER_ADDR_LEN); } error = ed_attach(dev); if (error) goto bad; if (sc->chip_type == ED_CHIP_TYPE_DL10019 || sc->chip_type == ED_CHIP_TYPE_DL10022) { /* Try to attach an MII bus, but ignore errors. */ ed_pccard_dl100xx_mii_reset(sc); (void)mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); } else if (sc->chip_type == ED_CHIP_TYPE_AX88190 || sc->chip_type == ED_CHIP_TYPE_AX88790 || sc->chip_type == ED_CHIP_TYPE_TC5299J) { error = mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); goto bad; } } if (sc->miibus != NULL) { sc->sc_tick = ed_pccard_tick; sc->sc_mediachg = ed_pccard_mediachg; sc->sc_media_ioctl = ed_pccard_media_ioctl; ed_pccard_kick_phy(sc); } else { ed_gen_ifmedia_init(sc); } if (modem_rid != -1) ed_pccard_add_modem(dev); error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, NULL, edintr, sc, &sc->irq_handle); if (error) { device_printf(dev, "setup intr failed %d \n", error); goto bad; } return (0); bad: ed_detach(dev); return (error); }
static int rp_probe(device_t dev) { int unit; CONTROLLER_t *controller; int num_aiops; CONTROLLER_t *ctlp; int retval; /* * We have no PnP RocketPort cards. * (At least according to LINT) */ if (isa_get_logicalid(dev) != 0) return (ENXIO); /* We need IO port resource to configure an ISA device. */ if (bus_get_resource_count(dev, SYS_RES_IOPORT, 0) == 0) return (ENXIO); unit = device_get_unit(dev); if (unit >= 4) { device_printf(dev, "rpprobe: unit number %d invalid.\n", unit); return (ENXIO); } device_printf(dev, "probing for RocketPort(ISA) unit %d.\n", unit); ctlp = device_get_softc(dev); bzero(ctlp, sizeof(*ctlp)); ctlp->dev = dev; ctlp->aiop2rid = rp_isa_aiop2rid; ctlp->aiop2off = rp_isa_aiop2off; ctlp->ctlmask = rp_isa_ctlmask; /* The IO ports of AIOPs for an ISA controller are discrete. */ ctlp->io_num = 1; ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * MAX_AIOPS_PER_BOARD, M_DEVBUF, M_NOWAIT | M_ZERO); ctlp->io = malloc(sizeof(*(ctlp->io)) * MAX_AIOPS_PER_BOARD, M_DEVBUF, M_NOWAIT | M_ZERO); if (ctlp->io_rid == NULL || ctlp->io == NULL) { device_printf(dev, "rp_attach: Out of memory.\n"); retval = ENOMEM; goto nogo; } ctlp->bus_ctlp = malloc(sizeof(ISACONTROLLER_t) * 1, M_DEVBUF, M_NOWAIT | M_ZERO); if (ctlp->bus_ctlp == NULL) { device_printf(dev, "rp_attach: Out of memory.\n"); retval = ENOMEM; goto nogo; } ctlp->io_rid[0] = 0; if (rp_controller != NULL) { controller = rp_controller; ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 0x40, RF_ACTIVE); } else { controller = rp_controller = ctlp; ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 0x44, RF_ACTIVE); } if (ctlp->io[0] == NULL) { device_printf(dev, "rp_attach: Resource not available.\n"); retval = ENXIO; goto nogo; } num_aiops = sInitController(ctlp, controller, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0); if (num_aiops <= 0) { device_printf(dev, "board%d init failed.\n", unit); retval = ENXIO; goto nogo; } if (rp_controller == NULL) rp_controller = controller; rp_nisadevs++; device_set_desc(dev, "RocketPort ISA"); return (0); nogo: rp_isareleaseresource(ctlp); return (retval); }
/****************************************************************************** agtiapi_InitResource() Purpose: Mapping PCI memory space Allocate and initialize per card based resource Parameters: ag_card_info_t *pCardInfo (IN) Return: AGTIAPI_SUCCESS - success AGTIAPI_FAIL - fail Note: ******************************************************************************/ STATIC agBOOLEAN agtiapi_InitResource( ag_card_info_t *thisCardInst ) { struct agtiapi_softc *pmsc = thisCardInst->pCard; device_t devx = thisCardInst->pPCIDev; //AGTIAPI_PRINTK( "agtiapi_InitResource: begin; pointer values %p / %p \n", // devx, thisCardInst ); // no IO mapped card implementation, we'll implement memory mapping if( agtiapi_typhAlloc( thisCardInst ) == AGTIAPI_FAIL ) { printf( "agtiapi_InitResource: failed call to agtiapi_typhAlloc \n" ); return AGTIAPI_FAIL; } AGTIAPI_PRINTK( "agtiapi_InitResource: dma alloc MemSpan %p -- %p\n", (void*) pmsc->typh_busaddr, (void*) ( (U32_64)pmsc->typh_busaddr + pmsc->typhn ) ); // logical BARs for SPC: // bar 0 and 1 - logical BAR0 // bar 2 and 3 - logical BAR1 // bar4 - logical BAR2 // bar5 - logical BAR3 // Skiping the assignments for bar 1 and bar 3 (making bar 0, 2 64-bit): U32 bar; U32 lBar = 0; // logicalBar for (bar = 0; bar < PCI_NUMBER_BARS; bar++) { if ((bar==1) || (bar==3)) continue; thisCardInst->pciMemBaseRIDSpc[lBar] = PCIR_BAR(bar); thisCardInst->pciMemBaseRscSpc[lBar] = bus_alloc_resource_any( devx, SYS_RES_MEMORY, &(thisCardInst->pciMemBaseRIDSpc[lBar]), RF_ACTIVE ); AGTIAPI_PRINTK( "agtiapi_InitResource: bus_alloc_resource_any rtn %p \n", thisCardInst->pciMemBaseRscSpc[lBar] ); if ( thisCardInst->pciMemBaseRscSpc[lBar] != NULL ) { thisCardInst->pciMemVirtAddrSpc[lBar] = (caddr_t)rman_get_virtual( thisCardInst->pciMemBaseRscSpc[lBar] ); thisCardInst->pciMemBaseSpc[lBar] = bus_get_resource_start( devx, SYS_RES_MEMORY, thisCardInst->pciMemBaseRIDSpc[lBar]); thisCardInst->pciMemSizeSpc[lBar] = bus_get_resource_count( devx, SYS_RES_MEMORY, thisCardInst->pciMemBaseRIDSpc[lBar] ); AGTIAPI_PRINTK( "agtiapi_InitResource: PCI: bar %d, lBar %d " "VirtAddr=%lx, len=%d\n", bar, lBar, (long unsigned int)thisCardInst->pciMemVirtAddrSpc[lBar], thisCardInst->pciMemSizeSpc[lBar] ); } else { thisCardInst->pciMemVirtAddrSpc[lBar] = 0; thisCardInst->pciMemBaseSpc[lBar] = 0; thisCardInst->pciMemSizeSpc[lBar] = 0; } lBar++; } thisCardInst->pciMemVirtAddr = thisCardInst->pciMemVirtAddrSpc[0]; thisCardInst->pciMemSize = thisCardInst->pciMemSizeSpc[0]; thisCardInst->pciMemBase = thisCardInst->pciMemBaseSpc[0]; // Allocate all TI data structure required resources. // tiLoLevelResource U32 numVal; ag_resource_info_t *pRscInfo; pRscInfo = &thisCardInst->tiRscInfo; pRscInfo->tiLoLevelResource.loLevelOption.pciFunctionNumber = pci_get_function( devx ); struct timeval tv; tv.tv_sec = 1; tv.tv_usec = 0; int ticksPerSec; ticksPerSec = tvtohz( &tv ); int uSecPerTick = 1000000/USEC_PER_TICK; if (pRscInfo->tiLoLevelResource.loLevelMem.count != 0) { //AGTIAPI_INIT("agtiapi_InitResource: loLevelMem count = %d\n", // pRscInfo->tiLoLevelResource.loLevelMem.count); // adjust tick value to meet Linux requirement pRscInfo->tiLoLevelResource.loLevelOption.usecsPerTick = uSecPerTick; AGTIAPI_PRINTK( "agtiapi_InitResource: " "pRscInfo->tiLoLevelResource.loLevelOption.usecsPerTick" " 0x%x\n", pRscInfo->tiLoLevelResource.loLevelOption.usecsPerTick ); for( numVal = 0; numVal < pRscInfo->tiLoLevelResource.loLevelMem.count; numVal++ ) { if( pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength == 0 ) { AGTIAPI_PRINTK("agtiapi_InitResource: skip ZERO %d\n", numVal); continue; } // check for 64 bit alignment if ( pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment < AGTIAPI_64BIT_ALIGN ) { AGTIAPI_PRINTK("agtiapi_InitResource: set ALIGN %d\n", numVal); pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment = AGTIAPI_64BIT_ALIGN; } if( ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & (BIT(0) | BIT(1))) == TI_DMA_MEM) || ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & (BIT(0) | BIT(1))) == TI_CACHED_DMA_MEM)) { if ( thisCardInst->dmaIndex >= sizeof(thisCardInst->tiDmaMem) / sizeof(thisCardInst->tiDmaMem[0]) ) { AGTIAPI_PRINTK( "Invalid dmaIndex %d ERROR\n", thisCardInst->dmaIndex ); return AGTIAPI_FAIL; } thisCardInst->tiDmaMem[thisCardInst->dmaIndex].type = #ifdef CACHED_DMA pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & (BIT(0) | BIT(1)); #else TI_DMA_MEM; #endif if( agtiapi_MemAlloc( thisCardInst, &thisCardInst->tiDmaMem[thisCardInst->dmaIndex].dmaVirtAddr, &thisCardInst->tiDmaMem[thisCardInst->dmaIndex].dmaPhysAddr, &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal]. physAddrUpper, &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal]. physAddrLower, pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, thisCardInst->tiDmaMem[thisCardInst->dmaIndex].type, pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment) != AGTIAPI_SUCCESS ) { return AGTIAPI_FAIL; } thisCardInst->tiDmaMem[thisCardInst->dmaIndex].memSize = pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength; //AGTIAPI_INIT("agtiapi_InitResource: LoMem %d dmaIndex=%d DMA virt" // " %p, phys 0x%x, length %d align %d\n", // numVal, pCardInfo->dmaIndex, // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].physAddrLower, // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment); thisCardInst->dmaIndex++; } else if ( (pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & (BIT(0) | BIT(1))) == TI_CACHED_MEM) { if (thisCardInst->cacheIndex >= sizeof(thisCardInst->tiCachedMem) / sizeof(thisCardInst->tiCachedMem[0])) { AGTIAPI_PRINTK( "Invalid cacheIndex %d ERROR\n", thisCardInst->cacheIndex ); return AGTIAPI_FAIL; } if ( agtiapi_MemAlloc( thisCardInst, &thisCardInst->tiCachedMem[thisCardInst->cacheIndex], (vm_paddr_t *)agNULL, &pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, (U32 *)agNULL, (U32 *)agNULL, pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, TI_CACHED_MEM, pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment) != AGTIAPI_SUCCESS ) { return AGTIAPI_FAIL; } //AGTIAPI_INIT("agtiapi_InitResource: LoMem %d cacheIndex=%d CACHED " // "vaddr %p / %p, length %d align %d\n", // numVal, pCardInfo->cacheIndex, // pCardInfo->tiCachedMem[pCardInfo->cacheIndex], // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].virtPtr, // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].totalLength, // pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].alignment); thisCardInst->cacheIndex++; } else if ( ((pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type & (BIT(0) | BIT(1))) == TI_DMA_MEM_CHIP)) { // not expecting this case, print warning that should get attention printf( "RED ALARM: we need a BAR for TI_DMA_MEM_CHIP, ignoring!" ); } else { printf( "agtiapi_InitResource: Unknown required memory type %d " "ERROR!\n", pRscInfo->tiLoLevelResource.loLevelMem.mem[numVal].type); return AGTIAPI_FAIL; } } } // end: TI data structure resources ... // begin: tiInitiatorResource if ( pmsc->flags & AGTIAPI_INITIATOR ) { if ( pRscInfo->tiInitiatorResource.initiatorMem.count != 0 ) { //AGTIAPI_INIT("agtiapi_InitResource: initiatorMem count = %d\n", // pRscInfo->tiInitiatorResource.initiatorMem.count); numVal = (U32)( pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick / uSecPerTick ); if( pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick % uSecPerTick > 0 ) pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick = (numVal + 1) * uSecPerTick; else pRscInfo->tiInitiatorResource.initiatorOption.usecsPerTick = numVal * uSecPerTick; for ( numVal = 0; numVal < pRscInfo->tiInitiatorResource.initiatorMem.count; numVal++ ) { // check for 64 bit alignment if( pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. alignment < AGTIAPI_64BIT_ALIGN ) { pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. alignment = AGTIAPI_64BIT_ALIGN; } if( thisCardInst->cacheIndex >= sizeof( thisCardInst->tiCachedMem) / sizeof( thisCardInst->tiCachedMem[0])) { AGTIAPI_PRINTK( "Invalid cacheIndex %d ERROR\n", thisCardInst->cacheIndex ); return AGTIAPI_FAIL; } // initiator memory is cached, no check is needed if( agtiapi_MemAlloc( thisCardInst, (void *)&thisCardInst->tiCachedMem[thisCardInst->cacheIndex], (vm_paddr_t *)agNULL, &pRscInfo->tiInitiatorResource.initiatorMem. tdCachedMem[numVal].virtPtr, (U32 *)agNULL, (U32 *)agNULL, pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. totalLength, TI_CACHED_MEM, pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. alignment) != AGTIAPI_SUCCESS) { return AGTIAPI_FAIL; } // AGTIAPI_INIT("agtiapi_InitResource: IniMem %d cacheIndex=%d CACHED " // "vaddr %p / %p, length %d align 0x%x\n", // numVal, // pCardInfo->cacheIndex, // pCardInfo->tiCachedMem[pCardInfo->cacheIndex], // pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. // virtPtr, //pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. // totalLength, // pRscInfo->tiInitiatorResource.initiatorMem.tdCachedMem[numVal]. // alignment); thisCardInst->cacheIndex++; } } } // end: tiInitiatorResource // begin: tiTdSharedMem if (pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength != 0) { // check for 64 bit alignment if( pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment < AGTIAPI_64BIT_ALIGN ) { pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment = AGTIAPI_64BIT_ALIGN; } if( (pRscInfo->tiSharedMem.tdSharedCachedMem1.type & (BIT(0) | BIT(1))) == TI_DMA_MEM ) { if( thisCardInst->dmaIndex >= sizeof(thisCardInst->tiDmaMem) / sizeof(thisCardInst->tiDmaMem[0]) ) { AGTIAPI_PRINTK( "Invalid dmaIndex %d ERROR\n", thisCardInst->dmaIndex); return AGTIAPI_FAIL; } if( agtiapi_MemAlloc( thisCardInst, (void *)&thisCardInst-> tiDmaMem[thisCardInst->dmaIndex].dmaVirtAddr, &thisCardInst->tiDmaMem[thisCardInst->dmaIndex]. dmaPhysAddr, &pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, &pRscInfo->tiSharedMem.tdSharedCachedMem1. physAddrUpper, &pRscInfo->tiSharedMem.tdSharedCachedMem1. physAddrLower, pRscInfo->tiSharedMem.tdSharedCachedMem1. totalLength, TI_DMA_MEM, pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment) != AGTIAPI_SUCCESS ) return AGTIAPI_FAIL; thisCardInst->tiDmaMem[thisCardInst->dmaIndex].memSize = pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength + pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment; // printf( "agtiapi_InitResource: SharedMem DmaIndex=%d DMA " // "virt %p / %p, phys 0x%x, align %d\n", // thisCardInst->dmaIndex, // thisCardInst->tiDmaMem[thisCardInst->dmaIndex].dmaVirtAddr, // pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, // pRscInfo->tiSharedMem.tdSharedCachedMem1.physAddrLower, // pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment); thisCardInst->dmaIndex++; } else if( (pRscInfo->tiSharedMem.tdSharedCachedMem1.type & (BIT(0) | BIT(1))) == TI_CACHED_MEM ) { if( thisCardInst->cacheIndex >= sizeof(thisCardInst->tiCachedMem) / sizeof(thisCardInst->tiCachedMem[0]) ) { AGTIAPI_PRINTK( "Invalid cacheIndex %d ERROR\n", thisCardInst->cacheIndex); return AGTIAPI_FAIL; } if( agtiapi_MemAlloc( thisCardInst, (void *)&thisCardInst-> tiCachedMem[thisCardInst->cacheIndex], (vm_paddr_t *)agNULL, &pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, (U32 *)agNULL, (U32 *)agNULL, pRscInfo-> tiSharedMem.tdSharedCachedMem1.totalLength, TI_CACHED_MEM, pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment) != AGTIAPI_SUCCESS ) return AGTIAPI_FAIL; // printf( "agtiapi_InitResource: SharedMem cacheIndex=%d CACHED " // "vaddr %p / %p, length %d align 0x%x\n", // thisCardInst->cacheIndex, // thisCardInst->tiCachedMem[thisCardInst->cacheIndex], // pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, // pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength, // pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment); AGTIAPI_PRINTK( "agtiapi_InitResource: SharedMem cacheIndex=%d CACHED " "vaddr %p / %p, length %d align 0x%x\n", thisCardInst->cacheIndex, thisCardInst->tiCachedMem[thisCardInst->cacheIndex], pRscInfo->tiSharedMem.tdSharedCachedMem1.virtPtr, pRscInfo->tiSharedMem.tdSharedCachedMem1.totalLength, pRscInfo->tiSharedMem.tdSharedCachedMem1.alignment ); thisCardInst->cacheIndex++; } else { AGTIAPI_PRINTK( "agtiapi_InitResource: " "Unknown required memory type ERROR!\n" ); return AGTIAPI_FAIL; } } // end: tiTdSharedMem DELAY( 200000 ); // or use AGTIAPI_INIT_MDELAY(200); return AGTIAPI_SUCCESS; } // agtiapi_InitResource() ends here