static void mhl_init_reg_settings(bool mhl_disc_en) { mhl_i2c_reg_write(TX_PAGE_L1, 0x003D, 0x3F); msleep(50); mhl_i2c_reg_write(TX_PAGE_2, 0x0011, 0x01); mhl_i2c_reg_write(TX_PAGE_2, 0x0012, 0x11); mhl_i2c_reg_write(TX_PAGE_3, 0x0030, 0x10); mhl_i2c_reg_write(TX_PAGE_3, 0x0035, 0xAC); mhl_i2c_reg_write(TX_PAGE_3, 0x0031, 0x3C); mhl_i2c_reg_write(TX_PAGE_3, 0x0033, 0xD9); mhl_i2c_reg_write(TX_PAGE_3, 0x0037, 0x02); mhl_i2c_reg_write(TX_PAGE_L0, 0x0080, 0x00); mhl_i2c_reg_write(TX_PAGE_L0, 0x00F8, 0x0C); mhl_i2c_reg_write(TX_PAGE_L0, 0x0085, 0x02); mhl_i2c_reg_write(TX_PAGE_2, 0x0000, 0x00); mhl_i2c_reg_write(TX_PAGE_2, 0x0013, 0x60); mhl_i2c_reg_write(TX_PAGE_2, 0x0017, 0x03); mhl_i2c_reg_write(TX_PAGE_2, 0x001A, 0x20); mhl_i2c_reg_write(TX_PAGE_2, 0x0022, 0xE0); mhl_i2c_reg_write(TX_PAGE_2, 0x0023, 0xC0); mhl_i2c_reg_write(TX_PAGE_2, 0x0024, 0xA0); mhl_i2c_reg_write(TX_PAGE_2, 0x0025, 0x80); mhl_i2c_reg_write(TX_PAGE_2, 0x0026, 0x60); mhl_i2c_reg_write(TX_PAGE_2, 0x0027, 0x40); mhl_i2c_reg_write(TX_PAGE_2, 0x0028, 0x20); mhl_i2c_reg_write(TX_PAGE_2, 0x0029, 0x00); mhl_i2c_reg_write(TX_PAGE_2, 0x0031, 0x0A); mhl_i2c_reg_write(TX_PAGE_2, 0x0045, 0x06); mhl_i2c_reg_write(TX_PAGE_2, 0x004B, 0x06); mhl_i2c_reg_write(TX_PAGE_2, 0x004C, 0xE0); mhl_i2c_reg_write(TX_PAGE_2, 0x004D, 0x00); mhl_i2c_reg_write(TX_PAGE_L0, 0x0008, 0x35); mhl_i2c_reg_write(TX_PAGE_3, 0x0011, 0xAD); mhl_i2c_reg_write(TX_PAGE_3, 0x0014, 0x55); mhl_i2c_reg_write(TX_PAGE_3, 0x0015, 0x11); mhl_i2c_reg_write(TX_PAGE_3, 0x0017, 0x82); mhl_i2c_reg_write(TX_PAGE_3, 0x0018, 0x24); mhl_i2c_reg_write(TX_PAGE_3, 0x0013, 0x8C); if (mhl_disc_en) mhl_i2c_reg_write(TX_PAGE_3, 0x0010, 0x27); else mhl_i2c_reg_write(TX_PAGE_3, 0x0010, 0x26); mhl_i2c_reg_write(TX_PAGE_3, 0x0016, 0x20); mhl_i2c_reg_write(TX_PAGE_3, 0x0012, 0x86); if (mhl_msm_state->cur_state != POWER_STATE_D0_MHL) mhl_drive_hpd(HPD_DOWN); mhl_i2c_reg_write(TX_PAGE_3, 0x0000, 0x084); mhl_i2c_reg_write(TX_PAGE_L0, 0x000D, 0x1C); cbus_reset(); init_cbus_regs(); }
/* * Configure the initial reg settings */ static void mhl_init_reg_settings(bool mhl_disc_en) { /* * ============================================ * POWER UP * ============================================ */ /* Power up 1.2V core */ mhl_i2c_reg_write(TX_PAGE_L1, 0x003D, 0x3F); /* * Wait for the source power to be enabled * before enabling pll clocks. */ msleep(50); /* Enable Tx PLL Clock */ mhl_i2c_reg_write(TX_PAGE_2, 0x0011, 0x01); /* Enable Tx Clock Path and Equalizer */ mhl_i2c_reg_write(TX_PAGE_2, 0x0012, 0x11); /* Tx Source Termination ON */ mhl_i2c_reg_write(TX_PAGE_3, 0x0030, 0x10); /* Enable 1X MHL Clock output */ mhl_i2c_reg_write(TX_PAGE_3, 0x0035, 0xAC); /* Tx Differential Driver Config */ mhl_i2c_reg_write(TX_PAGE_3, 0x0031, 0x3C); mhl_i2c_reg_write(TX_PAGE_3, 0x0033, 0xD9); /* PLL Bandwidth Control */ mhl_i2c_reg_write(TX_PAGE_3, 0x0037, 0x02); /* * ============================================ * Analog PLL Control * ============================================ */ /* Enable Rx PLL clock */ mhl_i2c_reg_write(TX_PAGE_L0, 0x0080, 0x00); mhl_i2c_reg_write(TX_PAGE_L0, 0x00F8, 0x0C); mhl_i2c_reg_write(TX_PAGE_L0, 0x0085, 0x02); mhl_i2c_reg_write(TX_PAGE_2, 0x0000, 0x00); mhl_i2c_reg_write(TX_PAGE_2, 0x0013, 0x60); /* PLL Cal ref sel */ mhl_i2c_reg_write(TX_PAGE_2, 0x0017, 0x03); /* VCO Cal */ mhl_i2c_reg_write(TX_PAGE_2, 0x001A, 0x20); /* Auto EQ */ mhl_i2c_reg_write(TX_PAGE_2, 0x0022, 0xE0); mhl_i2c_reg_write(TX_PAGE_2, 0x0023, 0xC0); mhl_i2c_reg_write(TX_PAGE_2, 0x0024, 0xA0); mhl_i2c_reg_write(TX_PAGE_2, 0x0025, 0x80); mhl_i2c_reg_write(TX_PAGE_2, 0x0026, 0x60); mhl_i2c_reg_write(TX_PAGE_2, 0x0027, 0x40); mhl_i2c_reg_write(TX_PAGE_2, 0x0028, 0x20); mhl_i2c_reg_write(TX_PAGE_2, 0x0029, 0x00); /* Rx PLL Bandwidth 4MHz */ mhl_i2c_reg_write(TX_PAGE_2, 0x0031, 0x0A); /* Rx PLL Bandwidth value from I2C */ mhl_i2c_reg_write(TX_PAGE_2, 0x0045, 0x06); mhl_i2c_reg_write(TX_PAGE_2, 0x004B, 0x06); /* Manual zone control */ mhl_i2c_reg_write(TX_PAGE_2, 0x004C, 0xE0); /* PLL Mode value */ mhl_i2c_reg_write(TX_PAGE_2, 0x004D, 0x00); mhl_i2c_reg_write(TX_PAGE_L0, 0x0008, 0x35); /* * Discovery Control and Status regs * Setting De-glitch time to 50 ms (default) * Switch Control Disabled */ mhl_i2c_reg_write(TX_PAGE_3, 0x0011, 0xAD); /* 1.8V CBUS VTH */ mhl_i2c_reg_write(TX_PAGE_3, 0x0014, 0x55); /* RGND and single Discovery attempt */ mhl_i2c_reg_write(TX_PAGE_3, 0x0015, 0x11); /* Ignore VBUS */ mhl_i2c_reg_write(TX_PAGE_3, 0x0017, 0x82); mhl_i2c_reg_write(TX_PAGE_3, 0x0018, 0x24); /* Pull-up resistance off for IDLE state */ mhl_i2c_reg_write(TX_PAGE_3, 0x0013, 0x8C); /* Enable CBUS Discovery */ if (mhl_disc_en) /* Enable MHL Discovery */ mhl_i2c_reg_write(TX_PAGE_3, 0x0010, 0x27); else /* Disable MHL Discovery */ mhl_i2c_reg_write(TX_PAGE_3, 0x0010, 0x26); mhl_i2c_reg_write(TX_PAGE_3, 0x0016, 0x20); /* MHL CBUS Discovery - immediate comm. */ mhl_i2c_reg_write(TX_PAGE_3, 0x0012, 0x86); /* Do not force HPD to 0 during wake-up from D3 */ if (mhl_msm_state->cur_state != POWER_STATE_D0_MHL) mhl_drive_hpd(HPD_DOWN); /* Enable Auto Soft RESET */ mhl_i2c_reg_write(TX_PAGE_3, 0x0000, 0x084); /* HDMI Transcode mode enable */ mhl_i2c_reg_write(TX_PAGE_L0, 0x000D, 0x1C); cbus_reset(); init_cbus_regs(); }
/* * Configure the initial reg settings */ static void mhl_init_reg_settings(struct mhl_tx_ctrl *mhl_ctrl, bool mhl_disc_en) { uint8_t regval; /* * ============================================ * POWER UP * ============================================ */ struct i2c_client *client = mhl_ctrl->i2c_handle; /* Power up 1.2V core */ MHL_SII_PAGE1_WR(0x003D, 0x3F); /* Enable Tx PLL Clock */ MHL_SII_PAGE2_WR(0x0011, 0x01); /* Enable Tx Clock Path and Equalizer */ MHL_SII_PAGE2_WR(0x0012, 0x11); /* Tx Source Termination ON */ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10); /* Enable 1X MHL Clock output */ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL6, 0xBC); /* Tx Differential Driver Config */ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL2, 0x3C); MHL_SII_REG_NAME_WR(REG_MHLTX_CTL4, 0xC8); /* PLL Bandwidth Control */ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL7, 0x03); MHL_SII_REG_NAME_WR(REG_MHLTX_CTL8, 0x0A); /* * ============================================ * Analog PLL Control * ============================================ */ /* Enable Rx PLL clock */ MHL_SII_REG_NAME_WR(REG_TMDS_CCTRL, 0x08); MHL_SII_PAGE0_WR(0x00F8, 0x8C); MHL_SII_PAGE0_WR(0x0085, 0x02); MHL_SII_PAGE2_WR(0x0000, 0x00); regval = MHL_SII_PAGE2_RD(0x0005); regval &= ~BIT5; MHL_SII_PAGE2_WR(0x0005, regval); MHL_SII_PAGE2_WR(0x0013, 0x60); /* PLL Cal ref sel */ MHL_SII_PAGE2_WR(0x0017, 0x03); /* VCO Cal */ MHL_SII_PAGE2_WR(0x001A, 0x20); /* Auto EQ */ MHL_SII_PAGE2_WR(0x0022, 0xE0); MHL_SII_PAGE2_WR(0x0023, 0xC0); MHL_SII_PAGE2_WR(0x0024, 0xA0); MHL_SII_PAGE2_WR(0x0025, 0x80); MHL_SII_PAGE2_WR(0x0026, 0x60); MHL_SII_PAGE2_WR(0x0027, 0x40); MHL_SII_PAGE2_WR(0x0028, 0x20); MHL_SII_PAGE2_WR(0x0029, 0x00); /* Rx PLL Bandwidth 4MHz */ MHL_SII_PAGE2_WR(0x0031, 0x0A); /* Rx PLL Bandwidth value from I2C */ MHL_SII_PAGE2_WR(0x0045, 0x06); MHL_SII_PAGE2_WR(0x004B, 0x06); MHL_SII_PAGE2_WR(0x004C, 0x60); /* Manual zone control */ MHL_SII_PAGE2_WR(0x004C, 0xE0); /* PLL Mode value */ MHL_SII_PAGE2_WR(0x004D, 0x00); MHL_SII_PAGE0_WR(0x0008, 0x35); /* * Discovery Control and Status regs * Setting De-glitch time to 50 ms (default) * Switch Control Disabled */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL2, 0xAD); /* 1.8V CBUS VTH */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL5, 0x57); /* RGND and single Discovery attempt */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL6, 0x11); /* Ignore VBUS */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL8, 0x82); /* Enable CBUS Discovery */ if (mhl_disc_en) { MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x24); /* Enable MHL Discovery */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x27); /* Pull-up resistance off for IDLE state */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C); } else { MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x26); /* Disable MHL Discovery */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x26); MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C); } MHL_SII_REG_NAME_WR(REG_DISC_CTRL7, 0x20); /* MHL CBUS Discovery - immediate comm. */ MHL_SII_REG_NAME_WR(REG_DISC_CTRL3, 0x86); MHL_SII_PAGE3_WR(0x3C, 0x80); if (mhl_ctrl->cur_state != POWER_STATE_D3) MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT6 | BIT5 | BIT4, BIT4); /* Enable Auto Soft RESET */ MHL_SII_REG_NAME_WR(REG_SRST, 0x084); /* HDMI Transcode mode enable */ MHL_SII_PAGE0_WR(0x000D, 0x1C); cbus_reset(mhl_ctrl); init_cbus_regs(client); }