static void
cferes_identify(driver_t* driver, device_t parent)
{
device_t child;
int i;
struct resource *res;
int result;
int rid;
struct cferes_softc *sc;
uint64_t addr, len, type;
child = BUS_ADD_CHILD(parent, 100, "cferes", -1);
device_set_driver(child, driver);
sc = device_get_softc(child);
sc->rnum = 0;
for (i = 0; i < ~0U; i++) {
result = cfe_enummem(i, CFE_FLG_FULL_ARENA, &addr, &len, &type);
if (result < 0)
break;
if (type != CFE_MI_RESERVED) {
if (bootverbose)
printf("%s: skipping non reserved range 0x%0jx(%jd)\n",
device_getnameunit(child),
(uintmax_t)addr, (uintmax_t)len);
continue;
}
bus_set_resource(child, SYS_RES_MEMORY, sc->rnum, addr, len);
rid = sc->rnum;
res = bus_alloc_resource_any(child, SYS_RES_MEMORY, &rid, 0);
if (res == NULL) {
bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum);
continue;
}
sc->rid[sc->rnum] = rid;
sc->res[sc->rnum] = res;
sc->rnum++;
if (sc->rnum == MAX_CFE_RESERVATIONS)
break;
}
if (sc->rnum == 0) {
device_delete_child(parent, child);
return;
}
device_set_desc(child, "CFE reserved memory");
}
static void
mips_init(void)
{
int i, j, cfe_mem_idx, tmp;
uint64_t maxmem;
#ifdef CFE_ENV
cfe_env_init();
#endif
TUNABLE_INT_FETCH("boothowto", &boothowto);
if (boothowto & RB_VERBOSE)
bootverbose++;
#ifdef MAXMEM
tmp = MAXMEM;
#else
tmp = 0;
#endif
TUNABLE_INT_FETCH("hw.physmem", &tmp);
maxmem = (uint64_t)tmp * 1024;
/*
* XXX
* If we used vm_paddr_t consistently in pmap, etc., we could
* use 64-bit page numbers on !n64 systems, too, like i386
* does with PAE.
*/
#if !defined(__mips_n64)
if (maxmem == 0 || maxmem > 0xffffffff)
maxmem = 0xffffffff;
#endif
#ifdef CFE
/*
* Query DRAM memory map from CFE.
*/
physmem = 0;
cfe_mem_idx = 0;
for (i = 0; i < 10; i += 2) {
int result;
uint64_t addr, len, type;
result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type);
if (result < 0) {
phys_avail[i] = phys_avail[i + 1] = 0;
break;
}
KASSERT(type == CFE_MI_AVAILABLE,
("CFE DRAM region is not available?"));
if (bootverbose)
printf("cfe_enummem: 0x%016jx/%ju.\n", addr, len);
if (maxmem != 0) {
if (addr >= maxmem) {
printf("Ignoring %ju bytes of memory at 0x%jx "
"that is above maxmem %dMB\n",
len, addr,
(int)(maxmem / (1024 * 1024)));
continue;
}
if (addr + len > maxmem) {
printf("Ignoring %ju bytes of memory "
"that is above maxmem %dMB\n",
(addr + len) - maxmem,
(int)(maxmem / (1024 * 1024)));
len = maxmem - addr;
}
}
phys_avail[i] = addr;
if (i == 0 && addr == 0) {
/*
* If this is the first physical memory segment probed
* from CFE, omit the region at the start of physical
* memory where the kernel has been loaded.
*/
phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
}
phys_avail[i + 1] = addr + len;
physmem += len;
}
realmem = btoc(physmem);
#endif
for (j = 0; j < i; j++)
dump_avail[j] = phys_avail[j];
physmem = realmem;
init_param1();
init_param2(physmem);
mips_cpu_init();
/*
* Sibyte has a L1 data cache coherent with DMA. This includes
* on-chip network interfaces as well as PCI/HyperTransport bus
* masters.
*/
cpuinfo.cache_coherent_dma = TRUE;
/*
* XXX
* The kernel is running in 32-bit mode but the CFE is running in
* 64-bit mode. So the SR_KX bit in the status register is turned
* on by the CFE every time we call into it - for e.g. CFE_CONSOLE.
*
* This means that if get a TLB miss for any address above 0xc0000000
* and the SR_KX bit is set then we will end up in the XTLB exception
* vector.
*
* For now work around this by copying the TLB exception handling
* code to the XTLB exception vector.
*/
{
bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
mips_icache_sync_all();
mips_dcache_wbinv_all();
}
pmap_bootstrap();
mips_proc0_init();
mutex_init();
kdb_init();
#ifdef KDB
if (boothowto & RB_KDB)
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
#endif
}
static __init void prom_meminit(void)
{
u64 addr, size, type; /* regardless of 64BIT_PHYS_ADDR */
int mem_flags = 0;
unsigned int idx;
int rd_flag;
#ifdef CONFIG_BLK_DEV_INITRD
unsigned long initrd_pstart;
unsigned long initrd_pend;
initrd_pstart = CPHYSADDR(initrd_start);
initrd_pend = CPHYSADDR(initrd_end);
if (initrd_start &&
((initrd_pstart > MAX_RAM_SIZE)
|| (initrd_pend > MAX_RAM_SIZE))) {
panic("initrd out of addressable memory");
}
#endif /* INITRD */
for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE;
idx++) {
rd_flag = 0;
if (type == CFE_MI_AVAILABLE) {
/*
* See if this block contains (any portion of) the
* ramdisk
*/
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) {
if ((initrd_pstart > addr) &&
(initrd_pstart < (addr + size))) {
add_memory_region(addr,
initrd_pstart - addr,
BOOT_MEM_RAM);
rd_flag = 1;
}
if ((initrd_pend > addr) &&
(initrd_pend < (addr + size))) {
add_memory_region(initrd_pend,
(addr + size) - initrd_pend,
BOOT_MEM_RAM);
rd_flag = 1;
}
}
#endif
if (!rd_flag) {
if (addr > MAX_RAM_SIZE)
continue;
if (addr+size > MAX_RAM_SIZE)
size = MAX_RAM_SIZE - (addr+size) + 1;
/*
* memcpy/__copy_user prefetch, which
* will cause a bus error for
* KSEG/KUSEG addrs not backed by RAM.
* Hence, reserve some padding for the
* prefetch distance.
*/
if (size > 512)
size -= 512;
add_memory_region(addr, size, BOOT_MEM_RAM);
}
board_mem_region_addrs[board_mem_region_count] = addr;
board_mem_region_sizes[board_mem_region_count] = size;
board_mem_region_count++;
if (board_mem_region_count ==
SIBYTE_MAX_MEM_REGIONS) {
/*
* Too many regions. Need to configure more
*/
while(1);
}
}
}
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) {
add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
BOOT_MEM_RESERVED);
}
#endif
}
/*
* Do all the stuff that locore normally does before calling main().
*/
void
mach_init(long fwhandle, long magic, long bootdata, long reserved)
{
void *kernend, *p0;
u_long first, last;
extern char edata[], end[];
int i;
uint32_t config;
/* XXX this code must run on the target CPU */
config = mips3_cp0_config_read();
config &= ~MIPS3_CONFIG_K0_MASK;
config |= 0x05; /* XXX. cacheable coherent */
mips3_cp0_config_write(config);
/* Zero BSS. XXXCGD: uh, is this really necessary still? */
memset(edata, 0, end - edata);
/*
* Copy the bootinfo structure from the boot loader.
* this has to be done before mips_vector_init is
* called because we may need CFE's TLB handler
*/
if (magic == BOOTINFO_MAGIC)
memcpy(&bootinfo, (struct bootinfo_v1 *)bootdata,
sizeof bootinfo);
else if (reserved == CFE_EPTSEAL) {
magic = BOOTINFO_MAGIC;
bzero(&bootinfo, sizeof bootinfo);
bootinfo.version = BOOTINFO_VERSION;
bootinfo.fwhandle = fwhandle;
bootinfo.fwentry = bootdata;
bootinfo.ssym = (vaddr_t)end;
bootinfo.esym = (vaddr_t)end;
}
kernend = (void *)mips_round_page(end);
#if NKSYMS || defined(DDB) || defined(LKM)
if (magic == BOOTINFO_MAGIC) {
ksym_start = (void *)bootinfo.ssym;
ksym_end = (void *)bootinfo.esym;
kernend = (void *)mips_round_page((vaddr_t)ksym_end);
}
#endif
consinit();
uvm_setpagesize();
/*
* Copy exception-dispatch code down to exception vector.
* Initialize locore-function vector.
* Clear out the I and D caches.
*/
mips_vector_init();
#ifdef DEBUG
printf("fwhandle=%08X magic=%08X bootdata=%08X reserved=%08X\n",
(u_int)fwhandle, (u_int)magic, (u_int)bootdata, (u_int)reserved);
#endif
strcpy(cpu_model, "sb1250");
if (magic == BOOTINFO_MAGIC) {
int idx;
int added;
uint64_t start, len, type;
cfe_init(bootinfo.fwhandle, bootinfo.fwentry);
cfe_present = 1;
idx = 0;
physmem = 0;
mem_cluster_cnt = 0;
while (cfe_enummem(idx, 0, &start, &len, &type) == 0) {
added = 0;
printf("Memory Block #%d start %08"PRIx64"X len %08"PRIx64"X: %s: ",
idx, start, len, (type == CFE_MI_AVAILABLE) ?
"Available" : "Reserved");
if ((type == CFE_MI_AVAILABLE) &&
(mem_cluster_cnt < VM_PHYSSEG_MAX)) {
/*
* XXX Ignore memory above 256MB for now, it
* XXX needs special handling.
*/
if (start < (256*1024*1024)) {
physmem += btoc(((int) len));
mem_clusters[mem_cluster_cnt].start =
(long) start;
mem_clusters[mem_cluster_cnt].size =
(long) len;
mem_cluster_cnt++;
added = 1;
}
}
if (added)
printf("added to map\n");
else
printf("not added to map\n");
idx++;
}
} else {
/*
* Handle the case of not being called from the firmware.
*/
/* XXX hardwire to 32MB; should be kernel config option */
physmem = 32 * 1024 * 1024 / 4096;
mem_clusters[0].start = 0;
mem_clusters[0].size = ctob(physmem);
mem_cluster_cnt = 1;
}
for (i = 0; i < sizeof(bootinfo.boot_flags); i++) {
switch (bootinfo.boot_flags[i]) {
case '\0':
break;
case ' ':
continue;
case '-':
while (bootinfo.boot_flags[i] != ' ' &&
bootinfo.boot_flags[i] != '\0') {
switch (bootinfo.boot_flags[i]) {
case 'a':
boothowto |= RB_ASKNAME;
break;
case 'd':
boothowto |= RB_KDB;
break;
case 's':
boothowto |= RB_SINGLE;
break;
}
i++;
}
}
}
/*
* Load the rest of the available pages into the VM system.
* The first chunk is tricky because we have to avoid the
* kernel, but the rest are easy.
*/
first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
last = mem_clusters[0].start + mem_clusters[0].size;
uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
VM_FREELIST_DEFAULT);
for (i = 1; i < mem_cluster_cnt; i++) {
first = round_page(mem_clusters[i].start);
last = mem_clusters[i].start + mem_clusters[i].size;
uvm_page_physload(atop(first), atop(last), atop(first),
atop(last), VM_FREELIST_DEFAULT);
}
/*
* Initialize error message buffer (at end of core).
*/
mips_init_msgbuf();
/*
* Allocate space for proc0's USPACE
*/
p0 = (void *)pmap_steal_memory(USPACE, NULL, NULL);
lwp0.l_addr = proc0paddr = (struct user *)p0;
lwp0.l_md.md_regs = (struct frame *)((char *)p0 + USPACE) - 1;
proc0paddr->u_pcb.pcb_context[11] =
MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
pmap_bootstrap();
/*
* Initialize debuggers, and break into them, if appropriate.
*/
#if NKSYMS || defined(DDB) || defined(LKM)
ksyms_init(((uintptr_t)ksym_end - (uintptr_t)ksym_start),
ksym_start, ksym_end);
#endif
if (boothowto & RB_KDB) {
#if defined(DDB)
Debugger();
#endif
}
}
static void
mips_init(void)
{
int i, j;
printf("entry: mips_init()\n");
#ifdef CFE
/*
* Query DRAM memory map from CFE.
*/
physmem = 0;
for (i = 0; i < 10; i += 2) {
int result;
uint64_t addr, len, type;
result = cfe_enummem(i / 2, 0, &addr, &len, &type);
if (result < 0) {
BCM_TRACE("There is no phys memory for: %d\n", i);
phys_avail[i] = phys_avail[i + 1] = 0;
break;
}
if (type != CFE_MI_AVAILABLE) {
BCM_TRACE("phys memory is not available: %d\n", i);
continue;
}
phys_avail[i] = addr;
if (i == 0 && addr == 0) {
/*
* If this is the first physical memory segment probed
* from CFE, omit the region at the start of physical
* memory where the kernel has been loaded.
*/
phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
}
BCM_TRACE("phys memory is available for: %d\n", i);
BCM_TRACE(" => addr = %jx\n", addr);
BCM_TRACE(" => len = %jd\n", len);
phys_avail[i + 1] = addr + len;
physmem += len;
}
BCM_TRACE("Total phys memory is : %ld\n", physmem);
realmem = btoc(physmem);
#endif
for (j = 0; j < i; j++)
dump_avail[j] = phys_avail[j];
physmem = realmem;
init_param1();
init_param2(physmem);
mips_cpu_init();
pmap_bootstrap();
mips_proc0_init();
mutex_init();
kdb_init();
#ifdef KDB
if (boothowto & RB_KDB)
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
#endif
}
