/*
* waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
* error and -2 for stall.
*/
static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
{
u16 csr;
int result = 1;
int timeout = CONFIG_MUSB_TIMEOUT;
while (result > 0) {
csr = readw(&musbr->txcsr);
if (csr & MUSB_CSR0_H_ERROR) {
csr &= ~MUSB_CSR0_H_ERROR;
writew(csr, &musbr->txcsr);
dev->status = USB_ST_CRC_ERR;
result = -1;
break;
}
switch (bit_mask) {
case MUSB_CSR0_TXPKTRDY:
if (!(csr & MUSB_CSR0_TXPKTRDY)) {
if (check_stall(MUSB_CONTROL_EP, 0)) {
dev->status = USB_ST_STALLED;
result = -2;
} else
result = 0;
}
break;
case MUSB_CSR0_RXPKTRDY:
if (check_stall(MUSB_CONTROL_EP, 0)) {
dev->status = USB_ST_STALLED;
result = -2;
} else
if (csr & MUSB_CSR0_RXPKTRDY)
result = 0;
break;
case MUSB_CSR0_H_REQPKT:
if (!(csr & MUSB_CSR0_H_REQPKT)) {
if (check_stall(MUSB_CONTROL_EP, 0)) {
dev->status = USB_ST_STALLED;
result = -2;
} else
result = 0;
}
break;
}
/* Check the timeout */
if (--timeout)
udelay(1);
else {
dev->status = USB_ST_CRC_ERR;
result = -1;
break;
}
}
return result;
}
/*
* waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
*/
static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
{
u16 csr;
int timeout = CONFIG_MUSB_TIMEOUT;
do {
if (check_stall(ep, 0)) {
dev->status = USB_ST_STALLED;
return 0;
}
csr = readw(&musbr->rxcsr);
if (csr & MUSB_RXCSR_H_ERROR) {
dev->status = USB_ST_CRC_ERR;
return 0;
}
/* Check the timeout */
if (--timeout)
udelay(1);
else {
dev->status = USB_ST_CRC_ERR;
return -1;
}
} while (!(csr & MUSB_RXCSR_RXPKTRDY));
return 1;
}
void ex()
{
struct inst * curr;
int i;
if( EX == EMPTY )
return;
curr = Instructions[EX];
if( EX_stall )
{
if( check_stall( (*curr).rs ) || check_stall( (*curr).rt ) ) /* check if stall still present */
{
fprintf( fout, "I%d-stall ", EX_count );
return;
}
else
{
IF1_stall = IF2_stall = ID_stall = EX_stall = NOSTALL;
}
}
if( (*curr).itype == DADD )
{
if( check_stall( (*curr).rs ) || check_stall( (*curr).rt ) )
{
IF1_stall = IF2_stall = ID_stall = EX_stall = STALL;
fprintf( fout, "I%d-stall ", EX_count );
return;
}
if( (*curr).rt == NOTUSED )
Registers[ RADDR((*curr).rd) ] = Registers[ RADDR((*curr).rs) ] + (*curr).value;
else
Registers[ RADDR((*curr).rd) ] = Registers[ RADDR((*curr).rs) ] + Registers[ RADDR((*curr).rt) ];
}
else if( (*curr).itype == SUB )
{
if( check_stall( (*curr).rs ) || check_stall( (*curr).rt ) )
{
IF1_stall = IF2_stall = ID_stall = EX_stall = STALL;
fprintf( fout, "I%d-stall ", EX_count );
return;
}
if( (*curr).rt == NOTUSED )
Registers[ RADDR((*curr).rd) ] = Registers[ RADDR((*curr).rs) ] - (*curr).value;
else
Registers[ RADDR((*curr).rd) ] = Registers[ RADDR((*curr).rs) ] - Registers[ RADDR((*curr).rt) ];
}
else if( (*curr).itype == BNEZ )
{
/* check condition */
if( check_stall( (*curr).rs ) )
{
IF1_stall = IF2_stall = ID_stall = EX_stall = STALL;
fprintf( fout, "I%d-stall ", EX_count );
return;
}
if( Registers[ RADDR((*curr).rs) ] != 0 )
{
for( i = 0; i < instcount; ++i )
{
if( strcmp( (*Instructions[i]).label, (*curr).btarget ) == 0 )
break;
}
if( i >= instcount ) /* unable to find branch target!!! */
return;
inst_counter = i;
/* flush pipeline */
flush = TRUE;
}
else
EX = EMPTY;
}
fprintf( fout, "I%d-EX ", EX_count );
}
