static void acpi_create_gnvs(global_nvs_t *gnvs)
{
gnvs->pcnt = dev_count_cpu();
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
/* TPM Present */
gnvs->tpmp = 1;
/* Enable DPTF */
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tact = ACTIVE_TEMPERATURE;
gnvs->dpte = 1;
#if CONFIG_CHROMEOS
chromeos_init_vboot(&(gnvs->chromeos));
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
}
static void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
struct soc_intel_apollolake_config *cfg;
struct device *dev = NB_DEV_ROOT;
/* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs));
if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
if (IS_ENABLED(CONFIG_CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_vboot(&gnvs->chromeos);
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = cfg->dptf_enable;
/* Assign address of PERST_0 if GPIO is defined in devicetree */
if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
}
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
gnvs->pcnt = dev_count_cpu();
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* CBMEM TOC */
gnvs->cmem = 0;
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
/* TPM Present */
gnvs->tpmp = 1;
#if CONFIG_CHROMEOS
chromeos_init_vboot(&(gnvs->chromeos));
/* Bayley Bay does not have a Chrome EC */
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
}
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
gnvs->s3u1 = 1;
/*
* Enable Front USB ports in S5 by default
* to be consistent with back port behavior
*/
gnvs->s5u0 = 1;
gnvs->s5u1 = 1;
/* CBMEM TOC */
gnvs->cmem = 0;
/* TPM Present */
gnvs->tpmp = 1;
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
// TODO(reinauer) this could move elsewhere?
chromeos_init_vboot(&(gnvs->chromeos));
/* Emerald Lake has no EC (?) */
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
acpi_update_thermal_table(gnvs);
}
static void acpi_create_gnvs(global_nvs_t *gnvs, igd_opregion_t *opregion)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* CBMEM TOC */
gnvs->cmem = (u32)get_cbmem_toc();
/* IGD Displays */
gnvs->ndid = 1;
gnvs->did[0] = 0x80000000;
gnvs->did[1] = 0x80000000;
gnvs->did[2] = 0x00000000;
gnvs->did[3] = 0x00000000;
gnvs->did[4] = 0x00000000;
#if CONFIG_CHROMEOS
// TODO(reinauer) this could move elsewhere?
chromeos_init_vboot(&(gnvs->chromeos));
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
/* IGD OpRegion Base Address */
gnvs->aslb = (u32)opregion;
acpi_update_thermal_table(gnvs);
// the lid is open by default.
gnvs->lids = 1;
}
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* CBMEM TOC */
gnvs->cmem = 0;
/* TPM Present */
gnvs->tpmp = 1;
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
// TODO(reinauer) this could move elsewhere?
chromeos_init_vboot(&(gnvs->chromeos));
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
acpi_update_thermal_table(gnvs);
}
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
gnvs_ = gnvs;
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
/* Enable Front USB ports in S3 by default */
gnvs->s3u0 = 1;
gnvs->s3u1 = 1;
/*
* Enable Front USB ports in S5 by default
* to be consistent with back port behavior
*/
gnvs->s5u0 = 1;
gnvs->s5u1 = 1;
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
// TODO(reinauer) this could move elsewhere?
chromeos_init_vboot(&(gnvs->chromeos));
#endif
acpi_update_thermal_table(gnvs);
// Stumpy has no arms^H^H^H^HEC.
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
