/**
* cik_sdma_enable - stop the async dma engines
*
* @adev: amdgpu_device pointer
* @enable: enable/disable the DMA MEs.
*
* Halt or unhalt the async dma engines (CIK).
*/
static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
{
u32 me_cntl;
int i;
if (!enable) {
cik_sdma_gfx_stop(adev);
cik_sdma_rlc_stop(adev);
}
for (i = 0; i < adev->sdma.num_instances; i++) {
me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
if (enable)
me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
else
me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
}
}
/**
* cik_sdma_enable - stop the async dma engines
*
* @rdev: radeon_device pointer
* @enable: enable/disable the DMA MEs.
*
* Halt or unhalt the async dma engines (CIK).
*/
void cik_sdma_enable(struct radeon_device *rdev, bool enable)
{
u32 me_cntl, reg_offset;
int i;
if (enable == false) {
cik_sdma_gfx_stop(rdev);
cik_sdma_rlc_stop(rdev);
}
for (i = 0; i < 2; i++) {
if (i == 0)
reg_offset = SDMA0_REGISTER_OFFSET;
else
reg_offset = SDMA1_REGISTER_OFFSET;
me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
if (enable)
me_cntl &= ~SDMA_HALT;
else
me_cntl |= SDMA_HALT;
WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
}
}