/* Delete file function:
* Delete a file
* Parameter(s):
* symbolic_file_name: a file name to be deleted.
* Return:
* Return 0 with success
* Return -1 with error (ie. No such file).
*/
int FileSystem53::deleteFile(string fileName)
{
int desc_index = search_dir(0, fileName);
if ( desc_index == -1 ) {
cout << "[email protected](): No such file" << endl;
return -1;
}
// check oft to see wheter it is opened
for (int i = 1; i < MAX_OPEN_FILE+1; i++)
{
if ( oft[i][0] != 0 && oft[i][0] == desc_index )
{
close(i);
}
}
// find the descriptor and mark the bytemap
for (int i = 1; i < DESCR_SIZE; i++)
{
int block_index = desc_table[desc_index][i];
if ( block_index != 0 && block_index > 6 )
{
desc_table[0][block_index] = 0;
}
}
clear_descriptor(desc_index);
// delecte the filename and related information from directory
int cursor = oft[0][OFT_CURRENT_POSITION_INDEX];
int start_pos = cursor;
int length = oft[0][1];
while ( cursor < (length+6) )
{
// filename's length
int desc_index = oft[0][cursor];
cursor++;
int nlength = oft[0][cursor];
//char buffer[nlength];
cursor++;
string name_buffer = "";
for (int i = 0; i < nlength; i++)
{
name_buffer += oft[0][cursor+i];
//buffer[i] = oft[index][cursor+i];
}
if ( fileName.compare(name_buffer) == 0 )
delete_dir(0, start_pos, nlength);
cursor += nlength-1;
}
return 0;
}
/**
* \brief initializes the hardware specific part of the descriptor to be used
* for general descriptors
*
* \param desc Xeon Phi descriptor
* \param dst destination address
* \param data Data payload for the request (request specific)
*/
inline void xeon_phi_dma_desc_fill_general(struct dma_descriptor *desc,
lpaddr_t dst,
uint64_t data)
{
uint8_t *d = dma_desc_get_desc_handle(desc);
clear_descriptor(d);
ASSERT_ALIGNED(dst);
xeon_phi_dma_desc_general_data_insert(d, data);
xeon_phi_dma_desc_general_dst_insert(d, dst);
xeon_phi_dma_desc_general_dtype_insert(d,
xeon_phi_dma_desc_general);
}
/*
* Free descriptor.
*
* Exchange the terminator and the first descriptor of the packet
* for hardware ascy...
*/
void dma_reclaim(struct dma_queue *q, struct dma_desc *desc)
{
struct dma_desc *tmpDesc, *last;
struct dma_desc tdesc;
/* 1. Set OWN bit to HW for all TDs to be added, clear ctrl and size */
tmpDesc = desc;
last = desc->lastAddr;
while (1) {
tmpDesc->status = AR9170_OWN_BITS_HW;
tmpDesc->ctrl = 0;
tmpDesc->totalLen = 0;
tmpDesc->dataSize = AR9170_BLOCK_SIZE;
/* TODO : Exception handle */
tmpDesc->lastAddr = tmpDesc;
if (tmpDesc == last)
break;
tmpDesc = tmpDesc->nextAddr;
}
/* 2. Next address of Last TD to be added = first TD */
tmpDesc->nextAddr = desc;
/* Link first TD to self */
desc->lastAddr = q->terminator;
/* 3. Copy first TD to be added to TTD */
copy_dma_desc(&tdesc, desc);
/* 4. Initialize new terminator */
clear_descriptor(desc);
/* 5. Copy TTD to last TD */
tdesc.status = 0;
copy_dma_desc((void *)q->terminator, (void *)&tdesc);
q->terminator->status |= AR9170_OWN_BITS_HW;
/* Update terminator pointer */
q->terminator = desc;
}
/*
* Put a complete packet into the tail of the Queue q.
* Exchange the terminator and the first descriptor of the packet
* for hardware ascy...
*/
void dma_put(struct dma_queue *q, struct dma_desc *desc)
{
struct dma_desc *tmpDesc;
struct dma_desc tdesc;
tmpDesc = desc;
while (1) {
/* update totalLen */
tmpDesc->totalLen = desc->totalLen;
/* 1. Set OWN bit to HW for all TDs to be added */
tmpDesc->status = AR9170_OWN_BITS_HW;
/* TODO : Exception handle */
tmpDesc->lastAddr = desc->lastAddr;
if (desc->lastAddr == tmpDesc)
break;
tmpDesc = tmpDesc->nextAddr;
}
/* 2. Next address of Last TD to be added = first TD */
desc->lastAddr->nextAddr = desc;
/* If there is only one descriptor, update pointer of last descriptor */
if (desc->lastAddr == desc)
desc->lastAddr = q->terminator;
/* 3. Copy first TD to be added to TTD */
copy_dma_desc(&tdesc, desc);
/* 4. Initialize new terminator */
clear_descriptor(desc);
/* 5. Copy TTD to last TD */
tdesc.status &= (~AR9170_OWN_BITS);
copy_dma_desc((void *)q->terminator, (void *)&tdesc);
q->terminator->status |= AR9170_OWN_BITS_HW;
/* Update terminator pointer */
q->terminator = desc;
}
/**
* \brief initializes the hardware specific part of the descriptor to be used
* for status descriptors
*
* \param desc Xeon Phi descriptor
* \param dst destination address
* \param data Data payload for the request (request specific)
* \param flags Descriptor flags
*/
inline void xeon_phi_dma_desc_fill_status(struct dma_descriptor *desc,
lpaddr_t dst,
uint64_t data,
uint32_t flags)
{
uint8_t *d = dma_desc_get_desc_handle(desc);
clear_descriptor(d);
ASSERT_ALIGNED(dst);
xeon_phi_dma_desc_status_data_insert(d, data);
xeon_phi_dma_desc_status_dst_insert(d, dst);
if (flags & XEON_PHI_DMA_DESC_FLAG_INTR) {
xeon_phi_dma_desc_status_intr_insert(d, 0x1);
}
xeon_phi_dma_desc_status_dtype_insert(d,
xeon_phi_dma_desc_status);
}
/**
* \brief initializes the hardware specific part of the descriptor to be used
* for memcpy descriptors
*
* \param desc Xeon Phi descriptor
* \param src Source address of the transfer
* \param dst destination address of the transfer
* \param size number of bytes to copy
* \param flags control flags
*
* XXX: this function assumes that the size of the descriptor has already been
* checked and must match the maximum transfer size of the channel
*/
inline void xeon_phi_dma_desc_fill_memcpy(struct dma_descriptor *desc,
lpaddr_t src,
lpaddr_t dst,
uint32_t size,
uint32_t flags)
{
uint8_t *d = dma_desc_get_desc_handle(desc);
clear_descriptor(d);
ASSERT_ALIGNED(src);
ASSERT_ALIGNED(dst);
ASSERT_ALIGNED(size);
if (flags & XEON_PHI_DMA_DESC_FLAG_INTR) {
xeon_phi_dma_desc_memcpy_intr_insert(d, 0x1);
}
if (flags & XEON_PHI_DMA_DESC_FLAG_TWB) {
xeon_phi_dma_desc_memcpy_twb_insert(d, 0x1);
}
if (flags & XEON_PHI_DMA_DESC_FLAG_C) {
xeon_phi_dma_desc_memcpy_c_insert(d, 0x1);
}
if (flags & XEON_PHI_DMA_DESC_FLAG_CO) {
xeon_phi_dma_desc_memcpy_co_insert(d, 0x1);
}
if (flags & XEON_PHI_DMA_DESC_FLAG_ECY) {
xeon_phi_dma_desc_memcpy_ecy_insert(d, 0x1);
}
xeon_phi_dma_desc_memcpy_intr_insert(d, 0x1);
xeon_phi_dma_desc_memcpy_twb_insert(d, 0x1);
xeon_phi_dma_desc_memcpy_src_insert(d, src);
xeon_phi_dma_desc_memcpy_dst_insert(d, dst);
xeon_phi_dma_desc_memcpy_length_insert(d, (size >> XEON_PHI_DMA_ALIGN_SHIFT));
xeon_phi_dma_desc_memcpy_dtype_insert(d, xeon_phi_dma_desc_memcpy);
}
/*
* - Init up_queue, down_queue, tx_queue[5], rx_queue.
* - Setup descriptors and data buffer address.
* - Ring descriptors rx_queue and down_queue by dma_reclaim().
*
* NOTE: LastAddr tempary point (same) to nextAddr after initialize.
* Because LastAddr is don't care in function dma_reclaim().
*/
void dma_init_descriptors(void)
{
unsigned int i, j;
for (i = 0; i < ARRAY_SIZE(dma_mem.terminator); i++)
clear_descriptor(&dma_mem.terminator[i]);
/* Assign terminators to DMA queues */
i = 0;
init_queue(&fw.pta.up_queue, &dma_mem.terminator[i++]);
init_queue(&fw.pta.down_queue, &dma_mem.terminator[i++]);
for (j = 0; j < __AR9170_NUM_TX_QUEUES; j++)
init_queue(&fw.wlan.tx_queue[j], &dma_mem.terminator[i++]);
init_queue(&fw.wlan.tx_retry, &dma_mem.terminator[i++]);
init_queue(&fw.wlan.rx_queue, &dma_mem.terminator[i++]);
fw.usb.int_desc = &dma_mem.terminator[i++];
fw.wlan.fw_desc = &dma_mem.terminator[i++];
for (j = 0; j < CARL9170_INTF_NUM; j++)
init_queue(&fw.wlan.cab_queue[j], &dma_mem.terminator[i++]);
BUG_ON(AR9170_TERMINATOR_NUMBER != i);
DBG("Blocks:%d [tx:%d, rx:%d] Terminators:%d/%d\n",
AR9170_BLOCK_NUMBER, AR9170_TX_BLOCK_NUMBER,
AR9170_RX_BLOCK_NUMBER, AR9170_TERMINATOR_NUMBER, i);
/* Init descriptors and memory blocks */
for (i = 0; i < AR9170_BLOCK_NUMBER; i++) {
fill_descriptor(&dma_mem.block[i], AR9170_BLOCK_SIZE, dma_mem.data[i].data);
if (i < AR9170_TX_BLOCK_NUMBER)
dma_reclaim(&fw.pta.down_queue, &dma_mem.block[i]);
else
dma_reclaim(&fw.wlan.rx_queue, &dma_mem.block[i]);
}
/* Set DMA address registers */
set(AR9170_PTA_REG_DN_DMA_ADDRH, (uint32_t) fw.pta.down_queue.head >> 16);
set(AR9170_PTA_REG_DN_DMA_ADDRL, (uint32_t) fw.pta.down_queue.head & 0xffff);
set(AR9170_PTA_REG_UP_DMA_ADDRH, (uint32_t) fw.pta.up_queue.head >> 16);
set(AR9170_PTA_REG_UP_DMA_ADDRL, (uint32_t) fw.pta.up_queue.head & 0xffff);
for (i = 0; i < __AR9170_NUM_TX_QUEUES; i++)
set_wlan_txq_dma_addr(i, (uint32_t) fw.wlan.tx_queue[i].head);
set(AR9170_MAC_REG_DMA_RXQ_ADDR, (uint32_t) fw.wlan.rx_queue.head);
fw.usb.int_desc->dataSize = AR9170_BLOCK_SIZE;
fw.usb.int_desc->dataAddr = (void *) &dma_mem.reserved.rsp;
memset(DESC_PAYLOAD(fw.usb.int_desc), 0xff,
AR9170_INT_MAGIC_HEADER_SIZE);
memset(DESC_PAYLOAD_OFF(fw.usb.int_desc, AR9170_INT_MAGIC_HEADER_SIZE),
0, AR9170_BLOCK_SIZE - AR9170_INT_MAGIC_HEADER_SIZE);
/* rsp is now available for use */
fw.usb.int_desc_available = 1;
memset(DESC_PAYLOAD(fw.wlan.fw_desc), 0, 128);
fw.wlan.fw_desc_available = 1;
}
/**
* \brief initializes the hardware specific part of the descriptor to be used
* for nop descriptors (null descriptors)
*
* \param desc Xeon Phi descriptor
*/
inline void xeon_phi_dma_desc_fill_nop(struct dma_descriptor *desc)
{
clear_descriptor(dma_desc_get_desc_handle(desc));
}