int main() {
char *first = "abcqwefdsdss";
char *second = "defcvbasdd";
char *third = "abc";
clearcache();
printf("distance between %s and %s is %d\n",
first, second, distance( first, second ) );
clearcache();
printf("distance between %s and %s is %d\n",
second, third, distance( second, third ) );
}
/*
* -a option:
* make <term>:<mask> outputs
* for use with quine, cover, etc.
*/
void
plaout(Node *tp)
{
register j, o, c;
Value x1, x2, d1, mask, li;
Value ibit, rdepend;
if (treeflag)
treeprint(tp);
if(chipname)
fprint(1, ".x %s\n", chipname->name);
for(o=1; o<=noutputs; o++) {
clrdepend();
compile(o);
getdepend();
if(ndepends > 31) {
if(outputs[o]->pin)
fprint(2, "too many inputs %d for %d\n",
ndepends, outputs[o]->pin);
else
fprint(2, "too many inputs %d for %s\n",
ndepends, outputs[o]->name);
#ifdef PLAN9
exits("too many inputs");
#else
exit(1);
#endif
}
mask = ~((Value)0) << ndepends;
rdepend = 0;
clearcache();
for(ibit = 1; (ibit & mask) == 0; ibit <<= 1) {
mask |= ibit;
for(li=0;;) {
x1 = vexec(li);
d1 = dcval;
x2 = vexec(li|ibit);
if(!(d1 & dcval))
if(x1^x2) {
rdepend |= ibit;
break;
}
li = ((li | mask) + 1) & ~mask;
if(!li)
break;
}
mask &= ~ibit;
}
poline(o, rdepend);
mask = ~rdepend;
j = 0;
for(li=0; ;) {
c = 0;
x1 = vexec(li);
if(x1)
c = ':';
if(dcval)
c = '%';
if(c) {
fprint(1, " %ld%c%ld",
take(li, rdepend), c,
take(~(Value) 0, rdepend));
j++;
if(j >= PERLINE) {
j = 0;
fprint(1, "\n");
}
}
li = ((li | mask) + 1) & ~mask;
if(!li)
break;
}
if(j)
fprint(1, "\n");
}
/* following is gone
* if output pins are the same,
* then make them be dependent on
* same inputs. this allows hand-crafted
* or gates by separate outputs.
for(i=1; i<=noutputs; i++) {
o = outputs[i]->pin;
if(o)
for(j=i+1; j<=noutputs; j++)
if(outputs[j]->pin == o) {
outputs[i]->depend |= outputs[j]->rdepend;
outputs[j]->depend = outputs[i]->depend;
}
}
for(o=0; o<noutputs; o++) {
depend = outputs[o+1]->depend;
rdepend = outputs[o+1]->rdepend;
obit = 1L << o;
clearcache();
} */
}
imagecache::~imagecache()
{
clearcache(ict_sys);
clearcache(ict_login);
clearcache(ict_map);
}
/*
* -r option:
* write out the eqn evaluation as a table
* suitable for putting in a rom.
*/
void
romout(Node *tp)
{
int j;
Value x, nperms, li;
int width; /* # bits per word */
int npline; /* # words per line */
int nline;
int line; /* output word # */
clearcache();
if (treeflag) {
treeprint(tp);
fprint(1, "\n\n\n");
#ifdef PLAN9
exits((char *) 0);
#else
exit(1);
#endif
}
nperms = 1L<<nleaves;
width = (hexflag) ? 4:3;
npline = (hexflag) ? 16:8;
if (promflag)
npline = 1;
if (noutputs > 16)
npline = 1;
line = 0;
nline = npline;
for(li=0;li<nperms;li++) {
/* vexec(li);*/
if (nline==npline && promflag==0) {
if (nperms < 10)
fprint(1, "%d: ",line);
else
if (nperms < 100)
fprint(1, "%2d: ",line);
else
if (nperms < 1000)
fprint(1, "%3d: ",line);
else
if (nperms < 10000)
fprint(1, "%4d: ",line);
}
x = 0;
if (hexflag)
fprint(1, "x"); else
fprint(1, "0");
for(j=noutputs-1; j>=0; j--) {
x <<= 1;
x += (rom[j] & 01);
if (j%width==0) {
if (hexflag)
fprint(1, "%x",x);
else
fprint(1, "%o",x);
x = 0;
}
}
nline--;
line++;
if (nline==0) {
fprint(1, "\n");
nline = npline;
} else {
fprint(1, " ");
}
}
}
//method for timing a memory access (memory read) of addresses
void Test2(struct args_st *arguments, size_t *timings)
{
size_t slot = 0;
struct perf_event_attr pe;
int perf_event_fd, addr;
long long cpu_cycles;
int i = 0;
//init the perf_event_attr before calling the syscall
memset(&pe, 0, sizeof(struct perf_event_attr));
pe.type = PERF_TYPE_HARDWARE;
pe.size = sizeof(struct perf_event_attr);
pe.config = PERF_COUNT_HW_CPU_CYCLES; //we are going to count the number of CPU cycles
pe.disabled = 1;
pe.exclude_kernel = 1;
pe.exclude_hv = 1;
perf_event_fd = perf_event_open(&pe, 0, -1, -1, 0);
if(perf_event_fd == -1)
{
fprintf(stderr, "Error opening leader %llx\n", pe.config);
exit(EXIT_FAILURE);
}
//Check overhead
printf("[+] Computing overhead\n");
long long overhead = 0, tmp = 0;
int N = 10000;
for(i = 0; i < N; i++)
{
ioctl(perf_event_fd, PERF_EVENT_IOC_RESET, 0);
ioctl(perf_event_fd, PERF_EVENT_IOC_ENABLE, 0);
ioctl(perf_event_fd, PERF_EVENT_IOC_DISABLE, 0);
read(perf_event_fd, &cpu_cycles, sizeof(long long));
overhead += cpu_cycles;
}
overhead /= N;
//Start probing addresses of the shared library from base_address to end_address
//in order to test the timing variations
char *probe;
i = 0;
printf("[+] Probing memread\n");
sched_yield();
for(probe = arguments->base_address; probe < arguments->end_address; probe += arguments->stride)
{
clearcache(arguments->base_address, arguments->end_address);
//start counting the cpu cycles
ioctl(perf_event_fd, PERF_EVENT_IOC_RESET, 0);
ioctl(perf_event_fd, PERF_EVENT_IOC_ENABLE, 0);
//do a memory read
memread(probe);
//stop counting the cpu cycles
ioctl(perf_event_fd, PERF_EVENT_IOC_DISABLE, 0);
//read the cpu cycles counter
read(perf_event_fd, &cpu_cycles, sizeof(long long));
//store it
timings[i++] = cpu_cycles - overhead;
}
sched_yield();
}
