static int bcm2835_clk_init(void)
{
int ret;
clks[dummy] = clk_fixed("dummy", 0);
clks[clk_ref_3] = clk_fixed("ref3", 3 * 1000 * 1000);
clks[clk_ref_1] = clk_fixed("ref1", 1 * 1000 * 1000);
ret = clk_register_clkdev(clks[dummy], "apb_pclk", NULL);
if (ret)
goto clk_err;
ret = clk_register_clkdev(clks[clk_ref_3], NULL, "uart0-pl0110");
if (ret)
goto clk_err;
ret = clk_register_clkdev(clks[clk_ref_1], NULL, "bcm2835-cs");
if (ret)
goto clk_err;
return 0;
clk_err:
return ret;
}
int __init mx1_clocks_init(void __iomem *regs, unsigned long fref)
{
clks[dummy] = clk_fixed("dummy", 0);
clks[clk32] = clk_fixed("clk32", fref);
clks[clk16m] = clk_fixed("clk16m", 16000000);
clks[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
clks[prem] = imx_clk_mux("prem", regs + CCM_CSCR, 16, 1, prem_sel_clks,
ARRAY_SIZE(prem_sel_clks));
clks[mpll] = imx_clk_pllv1("mpll", "clk32_premult", regs + CCM_MPCTL0);
clks[spll] = imx_clk_pllv1("spll", "prem", regs + CCM_SPCTL0);
clks[mcu] = imx_clk_divider("mcu", "clk32_premult", regs + CCM_CSCR, 15, 1);
clks[fclk] = imx_clk_divider("fclk", "mpll", regs + CCM_CSCR, 15, 1);
clks[hclk] = imx_clk_divider("hclk", "spll", regs + CCM_CSCR, 10, 4);
clks[clk48m] = imx_clk_divider("clk48m", "spll", regs + CCM_CSCR, 26, 3);
clks[per1] = imx_clk_divider("per1", "spll", regs + CCM_PCDR, 0, 4);
clks[per2] = imx_clk_divider("per2", "spll", regs + CCM_PCDR, 4, 4);
clks[per3] = imx_clk_divider("per3", "spll", regs + CCM_PCDR, 16, 7);
clks[clko] = imx_clk_mux("clko", regs + CCM_CSCR, 29, 3, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
clkdev_add_physbase(clks[per1], MX1_TIM1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1], MX1_TIM2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2], MX1_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1], MX1_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1], MX1_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2], MX1_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2], MX1_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[hclk], MX1_I2C_BASE_ADDR, NULL);
return 0;
}
int mvebu_coreclk_probe(struct device_d *dev)
{
struct device_node *np = dev->device_node;
const struct of_device_id *match;
const struct coreclk_soc_desc *desc;
const char *tclk_name = "tclk";
const char *cpuclk_name = "cpuclk";
void __iomem *base;
unsigned long rate;
int n;
match = of_match_node(mvebu_coreclk_ids, np);
if (!match)
return -EINVAL;
desc = (const struct coreclk_soc_desc *)match->data;
/* Get SAR base address */
base = dev_request_mem_region(dev, 0);
if (!base)
return -EINVAL;
/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
clk_data.clk_num = 2 + desc->num_ratios;
clk_data.clks = xzalloc(clk_data.clk_num * sizeof(struct clk *));
/* Register TCLK */
of_property_read_string_index(np, "clock-output-names", 0,
&tclk_name);
rate = desc->get_tclk_freq(base);
clk_data.clks[0] = clk_fixed(tclk_name, rate);
WARN_ON(IS_ERR(clk_data.clks[0]));
/* Register CPU clock */
of_property_read_string_index(np, "clock-output-names", 1,
&cpuclk_name);
rate = desc->get_cpu_freq(base);
clk_data.clks[1] = clk_fixed(cpuclk_name, rate);
WARN_ON(IS_ERR(clk_data.clks[1]));
/* Register fixed-factor clocks derived from CPU clock */
for (n = 0; n < desc->num_ratios; n++) {
const char *rclk_name = desc->ratios[n].name;
int mult, div;
of_property_read_string_index(np, "clock-output-names",
2+n, &rclk_name);
desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
clk_data.clks[2+n] = clk_fixed_factor(rclk_name, cpuclk_name,
mult, div, 0);
WARN_ON(IS_ERR(clk_data.clks[2+n]));
};
return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *base)
{
writel(0xffffffff, base + CCM_CCGR0);
writel(0xffffffff, base + CCM_CCGR1);
writel(0xffffffff, base + CCM_CCGR2);
writel(0xffffffff, base + CCM_CCGR3);
writel(0xffffffff, base + CCM_CCGR4);
writel(0xffffffff, base + CCM_CCGR5);
writel(0xffffffff, base + CCM_CCGR6);
writel(0xffffffff, base + CCM_CCGR7);
if (!IS_ENABLED(CONFIG_COMMON_CLK_OF_PROVIDER) || !dev->device_node) {
clks[IMX5_CLK_CKIL] = clk_fixed("ckil", 32768);
clks[IMX5_CLK_OSC] = clk_fixed("osc", 24000000);
}
clks[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
clks[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
clks[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
clks[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
clks[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
per_root_sel, ARRAY_SIZE(per_root_sel));
clks[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
clks[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
clks[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
clks[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
clks[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
clks[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
clks[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred",
"esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
clks[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf",
"esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
clks[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred",
"esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
clks[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf",
"esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
clks[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1,
4, 2, standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred",
"ecspi_sel", base + CCM_CSCDR2, 25, 3);
clks[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf",
"ecspi_pred", base + CCM_CSCDR2, 19, 6);
clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf",
"pll1_sw", base + CCM_CACRR, 0, 3);
}
static void __init rk3188_common_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *clk;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
/* Fixed-clock should be registered before all others */
clk=clk_fixed("xin24m",24000000);
if (IS_ERR(clk))
pr_warn("%s: could not register clock xin24m: %ld\n",
__func__, PTR_ERR(clk));
/* xin12m is created by an cru-internal divider */
clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0);
if (IS_ERR(clk))
pr_warn("%s: could not register clock xin12m: %ld\n",
__func__, PTR_ERR(clk));
clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0);
if (IS_ERR(clk))
pr_warn("%s: could not register clock usb480m: %ld\n",
__func__, PTR_ERR(clk));
rockchip_clk_register_branches(common_clk_branches,
ARRAY_SIZE(common_clk_branches));
rockchip_clk_protect_critical(rk3188_critical_clocks,
ARRAY_SIZE(rk3188_critical_clocks));
}
static void socfpga_mmc_init(void)
{
clks[mmc] = clk_fixed("mmc", 400000000);
clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL);
add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K,
IORESOURCE_MEM, &mmc_pdata);
}
static void socfpga_timer_init(void)
{
clks[timer] = clk_fixed("timer", 200000000);
clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100,
IORESOURCE_MEM, NULL);
}
static void v2m_clk_init(void)
{
struct clk *clk;
int i;
clk = clk_fixed("dummy_apb_pclk", 0);
clk_register_clkdev(clk, "apb_pclk", NULL);
clk = clk_fixed("mb:sp804_clk", 1000000);
clk_register_clkdev(clk, NULL, "sp804");
clk = clk_fixed("mb:osc2", 24000000);
for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]);
}
static void socfpga_uart_init(void)
{
clks[uart] = clk_fixed("uart", 100000000);
clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM |
IORESOURCE_MEM_8BIT, &uart_pdata);
}
static __maybe_unused void socfpga_qspi_init(void)
{
clks[qspi_clk] = clk_fixed("qspi_clk", 370000000);
clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL);
clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL);
add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS,
CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata);
}
static struct clk *socfpga_fixed_clk(struct device_node *node)
{
uint32_t f = 0;
of_property_read_u32(node, "clock-frequency", &f);
return clk_fixed(node->name, f);
}
static int imx31_ccm_probe(struct device_d *dev)
{
void __iomem *base;
base = dev_request_mem_region(dev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
writel(0xffffffff, base + CCM_CGR0);
writel(0xffffffff, base + CCM_CGR1);
writel(0xffffffff, base + CCM_CGR2);
clks[ckih] = clk_fixed("ckih", 26000000);
clks[ckil] = clk_fixed("ckil", 32768);
clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL);
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SRPCTL);
clks[upll] = imx_clk_pllv1("upll", "ckih", base + CCM_UPCTL);
clks[mcu_main] = imx_clk_mux("mcu_main", base + CCM_PMCR0, 31, 1,
mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
clks[hsp] = imx_clk_divider("hsp", "mcu_main", base + CCM_PDR0, 11, 3);
clks[ahb] = imx_clk_divider("ahb", "mcu_main", base + CCM_PDR0, 3, 3);
clks[nfc] = imx_clk_divider("nfc", "ahb", base + CCM_PDR0, 8, 3);
clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_PDR0, 6, 2);
clks[per_div] = imx_clk_divider("per_div", "upll", base + CCM_PDR0, 16, 5);
clks[per] = imx_clk_mux("per", base + CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
clkdev_add_physbase(clks[per], MX31_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_I2C3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX31_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX31_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX31_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[hsp], MX31_IPU_CTRL_BASE_ADDR, NULL);
return 0;
}
static struct clk *rpi_register_firmware_clock(u32 clock_id, const char *name)
{
BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
int ret;
BCM2835_MBOX_INIT_HDR(msg);
BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
msg->get_clock_rate.body.req.clock_id = clock_id;
ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
if (ret)
return ERR_PTR(ret);
return clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
}
static int zynq_clock_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *slcr_base;
unsigned long ps_clk_rate = 33333330;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
slcr_base = IOMEM(iores->start);
clks[ps_clk] = clk_fixed("ps_clk", ps_clk_rate);
clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100);
clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104);
clks[io_pll] = zynq_pll_clk(ZYNQ_PLL_IO, "io_pll", slcr_base + 0x108);
clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0, 0, 0);
clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1, 0, 0);
clks[gem0] = clk_gate("gem0", "io_pll", slcr_base + 0x140, 0, 0, 0);
clks[gem1] = clk_gate("gem1", "io_pll", slcr_base + 0x144, 1, 0, 0);
clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
slcr_base + 0x120, slcr_base + 0x1C4);
clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
slcr_base + 0x120, slcr_base + 0x1C4);
clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
slcr_base + 0x120, slcr_base + 0x1C4);
clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
slcr_base + 0x120, slcr_base + 0x1C4);
clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
clk_register_clkdev(clks[gem0], NULL, "macb0");
clk_register_clkdev(clks[gem1], NULL, "macb1");
clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
return 0;
}
static int armada_370_init_clocks(void)
{
u32 val = readl(ARMADA_370_XP_SAR_BASE + SAR_LOW);
unsigned int rate;
/*
* On Armada 370, the TCLK frequency can be either
* 166 Mhz or 200 Mhz
*/
if ((val & SAR_TCLK_FREQ) == SAR_TCLK_FREQ)
rate = 200000000;
else
rate = 166000000;
tclk = clk_fixed("tclk", rate);
return clk_register_clkdev(tclk, NULL, "mvebu-timer");
}
/*
* Dove TCLK sample-at-reset configuation
*
* SAR0[24:23] : TCLK frequency
* 0 = 166 MHz
* 1 = 125 MHz
* others reserved.
*/
static int dove_init_clocks(void)
{
uint32_t strap, sar = readl(DOVE_SAR_BASE + SAR0);
unsigned int rate;
strap = (sar & TCLK_FREQ_MASK) >> TCLK_FREQ_SHIFT;
switch (strap) {
case 0:
rate = 166666667;
break;
case 1:
rate = 125000000;
break;
default:
panic("Unknown TCLK strapping %d\n", strap);
}
tclk = clk_fixed("tclk", rate);
return clk_register_clkdev(tclk, NULL, "orion-timer");
}
static int rpi_register_clkdev(u32 clock_id, const char *name)
{
BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg);
struct clk *clk;
int ret;
BCM2835_MBOX_INIT_HDR(msg);
BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE);
msg->get_clock_rate.body.req.clock_id = clock_id;
ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
if (ret)
return ret;
clk = clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz);
if (IS_ERR(clk))
return PTR_ERR(clk);
if (!clk_register_clkdev(clk, NULL, name))
return -ENODEV;
return 0;
}
static int imx25_ccm_probe(struct device_d *dev)
{
struct resource *iores;
void __iomem *base;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
base = IOMEM(iores->start);
writel((1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 8) | (1 << 9) |
(1 << 10) | (1 << 15) | (1 << 19) | (1 << 21) | (1 << 22) |
(1 << 23) | (1 << 24) | (1 << 28),
base + CCM_CGCR0);
writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
(1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
(1 << 26) | (1 << 31),
base + CCM_CGCR1);
writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
(1 << 15) | (1 << 16) | (1 << 17) | (1 << 18),
base + CCM_CGCR2);
clks[dummy] = clk_fixed("dummy", 0);
clks[osc] = clk_fixed("osc", 24000000);
clks[mpll] = imx_clk_pllv1("mpll", "osc", base + CCM_MPCTL);
clks[upll] = imx_clk_pllv1("upll", "osc", base + CCM_UPCTL);
clks[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CCTL, 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
clks[cpu] = imx_clk_divider("cpu", "cpu_sel", base + CCM_CCTL, 30, 2);
clks[ahb] = imx_clk_divider("ahb", "cpu", base + CCM_CCTL, 28, 2);
clks[usb_div] = imx_clk_divider("usb_div", "upll", base + CCM_CCTL, 16, 6);
clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
clks[per0_sel] = imx_clk_mux("per0_sel", base + CCM_MCR, 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per1_sel] = imx_clk_mux("per1_sel", base + CCM_MCR, 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per2_sel] = imx_clk_mux("per2_sel", base + CCM_MCR, 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per3_sel] = imx_clk_mux("per3_sel", base + CCM_MCR, 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per4_sel] = imx_clk_mux("per4_sel", base + CCM_MCR, 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per5_sel] = imx_clk_mux("per5_sel", base + CCM_MCR, 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per6_sel] = imx_clk_mux("per6_sel", base + CCM_MCR, 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per7_sel] = imx_clk_mux("per7_sel", base + CCM_MCR, 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per8_sel] = imx_clk_mux("per8_sel", base + CCM_MCR, 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per9_sel] = imx_clk_mux("per9_sel", base + CCM_MCR, 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per10_sel] = imx_clk_mux("per10_sel", base + CCM_MCR, 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per11_sel] = imx_clk_mux("per11_sel", base + CCM_MCR, 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per12_sel] = imx_clk_mux("per12_sel", base + CCM_MCR, 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per13_sel] = imx_clk_mux("per13_sel", base + CCM_MCR, 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per14_sel] = imx_clk_mux("per14_sel", base + CCM_MCR, 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per15_sel] = imx_clk_mux("per15_sel", base + CCM_MCR, 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clks[per0] = imx_clk_divider("per0", "per0_sel", base + CCM_PCDR0, 0, 6);
clks[per1] = imx_clk_divider("per1", "per1_sel", base + CCM_PCDR0, 8, 6);
clks[per2] = imx_clk_divider("per2", "per2_sel", base + CCM_PCDR0, 16, 6);
clks[per3] = imx_clk_divider("per3", "per3_sel", base + CCM_PCDR0, 24, 6);
clks[per4] = imx_clk_divider("per4", "per4_sel", base + CCM_PCDR1, 0, 6);
clks[per5] = imx_clk_divider("per5", "per5_sel", base + CCM_PCDR1, 8, 6);
clks[per6] = imx_clk_divider("per6", "per6_sel", base + CCM_PCDR1, 16, 6);
clks[per7] = imx_clk_divider("per7", "per7_sel", base + CCM_PCDR1, 24, 6);
clks[per8] = imx_clk_divider("per8", "per8_sel", base + CCM_PCDR2, 0, 6);
clks[per9] = imx_clk_divider("per9", "per9_sel", base + CCM_PCDR2, 8, 6);
clks[per10] = imx_clk_divider("per10", "per10_sel", base + CCM_PCDR2, 16, 6);
clks[per11] = imx_clk_divider("per11", "per11_sel", base + CCM_PCDR2, 24, 6);
clks[per12] = imx_clk_divider("per12", "per12_sel", base + CCM_PCDR3, 0, 6);
clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6);
clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6);
clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6);
clks[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", base + CCM_CGCR0, 24);
clks[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", base + CCM_CGCR1, 29);
clks[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", base + CCM_CGCR0, 7);
clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_I2C3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per8], MX25_NFC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_ipg_per], MX25_LCDC_BASE_ADDR, "per");
clkdev_add_physbase(clks[lcdc_ipg], MX25_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[lcdc_ahb], MX25_LCDC_BASE_ADDR, "ahb");
return 0;
}
static int armada_xp_init_clocks(void)
{
/* On Armada XP, the TCLK frequency is always 250 Mhz */
tclk = clk_fixed("tclk", 250000000);
return 0;
}
static int imx27_ccm_probe(struct device_d *dev)
{
void __iomem *base;
base = dev_request_mem_region(dev, 0);
writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN |
PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN |
PCCR0_I2C2_EN | PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN |
PCCR0_GPT4_EN | PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN |
PCCR0_GPIO_EN | PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN |
PCCR0_CSPI1_EN,
base + CCM_PCCR0);
writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN |
PCCR1_HCLK_USB | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN |
PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN |
PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN,
base + CCM_PCCR1);
clks[dummy] = clk_fixed("dummy", 0);
clks[ckih] = clk_fixed("ckih", 26000000);
clks[ckil] = clk_fixed("ckil", 32768);
clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
clks[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
clks[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", base + CCM_CSCR, 4, 1,
mpll_osc_sel_clks,
ARRAY_SIZE(mpll_osc_sel_clks));
clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks,
ARRAY_SIZE(mpll_sel_clks));
clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0);
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
if (imx_silicon_revision() >= IMX_CHIP_REV_2_0) {
clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2);
clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
} else {
clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 9, 4);
clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CSCR, 8, 1);
}
clks[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + CCM_PCDR0, 6, 4);
clks[per1_div] = imx_clk_divider("per1_div", "mpll_main2", base + CCM_PCDR1, 0, 6);
clks[per2_div] = imx_clk_divider("per2_div", "mpll_main2", base + CCM_PCDR1, 8, 6);
clks[per3_div] = imx_clk_divider("per3_div", "mpll_main2", base + CCM_PCDR1, 16, 6);
clks[per4_div] = imx_clk_divider("per4_div", "mpll_main2", base + CCM_PCDR1, 24, 6);
clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 28, 3);
clks[cpu_sel] = imx_clk_mux("cpu_sel", base + CCM_CSCR, 15, 1, cpu_sel_clks,
ARRAY_SIZE(cpu_sel_clks));
clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
if (imx_silicon_revision() >= IMX_CHIP_REV_2_0)
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2);
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
clks[per3_gate] = imx_clk_gate("per3_gate", "per3_div", base + CCM_PCCR1, 8);
clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR1, 15);
clks[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", base + CCM_PCCR0, 14);
clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_GPT6_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per1_div], MX27_UART6_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX27_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, "per");
clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb");
clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
return 0;
}
static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
unsigned long rate_osc, unsigned long rate_ckih1,
unsigned long rate_ckih2)
{
writel(0xffffffff, base + CCM_CCGR0);
writel(0xffffffff, base + CCM_CCGR1);
writel(0xffffffff, base + CCM_CCGR2);
writel(0xffffffff, base + CCM_CCGR3);
writel(0xffffffff, base + CCM_CCGR4);
writel(0xffffffff, base + CCM_CCGR5);
writel(0xffffffff, base + CCM_CCGR6);
writel(0xffffffff, base + CCM_CCGR7);
clks[dummy] = clk_fixed("dummy", 0);
clks[ckil] = clk_fixed("ckil", rate_ckil);
clks[osc] = clk_fixed("osc", rate_osc);
clks[ckih1] = clk_fixed("ckih1", rate_ckih1);
clks[ckih2] = clk_fixed("ckih2", rate_ckih2);
clks[lp_apm] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clks[periph_apm] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
clks[main_bus] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
main_bus_sel, ARRAY_SIZE(main_bus_sel));
clks[per_lp_apm] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
clks[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
clks[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
clks[per_podf] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
clks[per_root] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
per_root_sel, ARRAY_SIZE(per_root_sel));
clks[ahb] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
clks[axi_a] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
clks[axi_b] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
clks[uart_root] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
clks[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
clks[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
clks[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
clks[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
clks[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
clks[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
clks[emi_sel] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
clks[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
clks[ecspi_sel] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
clks[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
clks[usboh3_sel] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
clks[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
clks[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
clks[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
clks[usb_phy_sel] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
clks[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
}
int __init mx28_clocks_init(void __iomem *regs)
{
clks[ref_xtal] = clk_fixed("ref_xtal", 24000000);
clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
clks[ssp0_gate] = mxs_clk_gate("ssp0_gate", "ssp0_sel", SSP0, 31);
clks[ssp1_gate] = mxs_clk_gate("ssp1_gate", "ssp1_sel", SSP1, 31);
clks[ssp2_gate] = mxs_clk_gate("ssp2_gate", "ssp2_sel", SSP2, 31);
clks[ssp3_gate] = mxs_clk_gate("ssp3_gate", "ssp3_sel", SSP3, 31);
clks[ssp0] = mxs_clk_div("ssp0", "ssp0_gate", SSP0, 0, 9, 29);
clks[ssp1] = mxs_clk_div("ssp1", "ssp1_gate", SSP1, 0, 9, 29);
clks[ssp2] = mxs_clk_div("ssp2", "ssp2_gate", SSP2, 0, 9, 29);
clks[ssp3] = mxs_clk_div("ssp3", "ssp3_gate", SSP3, 0, 9, 29);
clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
clks[fec_sleep] = mxs_clk_gate("fec_sleep", "hbus", ENET, 31);
clks[fec] = mxs_clk_gate("fec", "fec_sleep", ENET, 30);
clks[usb0_phy] = mxs_clk_gate("usb0_phy", "pll0", PLL0CTRL0, 18);
clks[usb1_phy] = mxs_clk_gate("usb1_phy", "pll1", PLL1CTRL0, 18);
clks[enet_out] = clk_gate("enet_out", "pll2", ENET, 18, 0, 0);
clks[lcdif_comp] = mxs_clk_lcdif("lcdif_comp", clks[ref_pix],
clks[lcdif_div], clks[lcdif]);
clk_set_rate(clks[ref_io0], 480000000);
clk_set_rate(clks[ref_io1], 480000000);
clk_set_parent(clks[ssp0_sel], clks[ref_io0]);
clk_set_parent(clks[ssp1_sel], clks[ref_io0]);
clk_set_parent(clks[ssp2_sel], clks[ref_io1]);
clk_set_parent(clks[ssp3_sel], clks[ref_io1]);
clk_set_rate(clks[ssp0], 96000000);
clk_set_rate(clks[ssp1], 96000000);
clk_set_rate(clks[ssp2], 96000000);
clk_set_rate(clks[ssp3], 96000000);
clk_set_parent(clks[lcdif_sel], clks[ref_pix]);
clk_enable(clks[enet_out]);
clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL);
clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL);
clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL);
clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL);
clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL);
clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL);
clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL);
clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL);
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM))
clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL);
return 0;
}
