void hsusb_clock_init(void)
{
int ret;
struct clk *iclk, *cclk;
ret = clk_get_set_enable("usb_iface_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
ASSERT(0);
}
/* Wait for the clocks to be stable since we are disabling soon after. */
mdelay(1);
iclk = clk_get("usb_iface_clk");
cclk = clk_get("usb_core_clk");
clk_disable(iclk);
clk_disable(cclk);
/* Wait for the clock disable to complete. */
mdelay(1);
/* Start the block reset for usb */
writel(1, USB_HS_BCR);
/* Wait for reset to complete. */
mdelay(1);
/* Take usb block out of reset */
writel(0, USB_HS_BCR);
/* Wait for the block to be brought out of reset. */
mdelay(1);
ret = clk_enable(iclk);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
ASSERT(0);
}
ret = clk_enable(cclk);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
ASSERT(0);
}
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
int ret;
char clk_name[64];
snprintf(clk_name, 64, "sdc%u_core_clk", interface);
if(freq == MMC_CLK_400KHZ)
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
}
else if(freq == MMC_CLK_200MHZ)
{
ret = clk_get_set_enable(clk_name, 200000000, 1);
}
else
{
dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
ASSERT(0);
}
if(ret)
{
dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
ASSERT(0);
}
}
void hdmi_clk_enable(void)
{
int ret;
/* Configure hdmi ahb clock */
ret = clk_get_set_enable("hdmi_ahb_clk", 0, 1);
if(ret) {
dprintf(CRITICAL, "failed to set hdmi_ahb_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure hdmi core clock */
ret = clk_get_set_enable("hdmi_core_clk", 19200000, 1);
if(ret) {
dprintf(CRITICAL, "failed to set hdmi_core_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure hdmi pixel clock */
ret = clk_get_set_enable("hdmi_extp_clk", 148500000, 1);
if(ret) {
dprintf(CRITICAL, "failed to set hdmi_extp_clk ret = %d\n", ret);
ASSERT(0);
}
}
/* Configure MDP clock */
void mdp_clock_init(void)
{
int ret;
/* Set MDP clock to 200MHz */
ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("mdss_mdp_clk_src", 75000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret);
ASSERT(0);
}
}
/* Enable all the bus clocks needed by MDP */
void mmss_bus_clocks_enable(void)
{
int ret;
/* Configure MMSSNOC AXI clock */
ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure MMSSNOC AXI clock */
ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure AXI clock */
ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
ASSERT(0);
}
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
int ret;
ret = clk_get_set_enable("uart3_iface_clk", 0, 1);
ret = clk_get_set_enable("uart3_core_clk", 7372800, 1);
}
/* enables usb30 interface and master clocks */
void clock_usb30_init(void)
{
int ret;
/* interface clock */
ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
ASSERT(0);
}
clock_usb30_gdsc_enable();
/* master clock */
ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
ASSERT(0);
}
/* Enable pmic diff clock */
pm8x41_diff_clock_ctrl(1);
}
void hsusb_clock_init(void)
{
int ret;
struct clk *iclk, *cclk;
ret = clk_get_set_enable("usb_iface_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
ASSERT(0);
}
mdelay(20);
iclk = clk_get("usb_iface_clk");
cclk = clk_get("usb_core_clk");
/* Disable USB all clock init */
writel(0, USB_BOOT_CLOCK_CTL);
clk_disable(iclk);
clk_disable(cclk);
mdelay(20);
/* Start the block reset for usb */
writel(1, USB_HS_BCR);
mdelay(20);
/* Take usb block out of reset */
writel(0, USB_HS_BCR);
mdelay(20);
ret = clk_enable(iclk);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
ASSERT(0);
}
ret = clk_enable(cclk);
if(ret)
{
dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
ASSERT(0);
}
}
/* Configure crypto engine clock */
void ce_clock_init(void)
{
/* Enable HCLK for CE */
clk_get_set_enable("ce1_pclk", 0, 1);
/* Enable core clk for CE */
clk_get_set_enable("ce1_clk", 0, 1);
}
/* Turn on MDP related clocks and pll's for MDP */
void mdp_clock_init(void)
{
/* Set MDP clock to 200MHz */
clk_get_set_enable("mdp_clk", 200000000, 1);
/* Seems to lose pixels without this from status 0x051E0048 */
clk_get_set_enable("lut_mdp", 0, 1);
}
/* Configure UART clock - based on the gsbi id */
void clock_config_uart_dm(uint8_t id)
{
char gsbi_uart_clk_id[64];
char gsbi_p_clk_id[64];
snprintf(gsbi_uart_clk_id, 64,"gsbi%u_uart_clk", id);
clk_get_set_enable(gsbi_uart_clk_id, 1843200, 1);
snprintf(gsbi_p_clk_id, 64,"gsbi%u_pclk", id);
clk_get_set_enable(gsbi_p_clk_id, 0, 1);
}
/* Configure i2c clock */
void clock_config_i2c(uint8_t id, uint32_t freq)
{
char gsbi_qup_clk_id[64];
char gsbi_p_clk_id[64];
snprintf(gsbi_qup_clk_id, 64,"gsbi%u_qup_clk", id);
clk_get_set_enable(gsbi_qup_clk_id, 24000000, 1);
snprintf(gsbi_p_clk_id, 64,"gsbi%u_pclk", id);
clk_get_set_enable(gsbi_p_clk_id, 0, 1);
}
void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
{
int ret;
/* Configure Byte clock -autopll- This will not change because
byte clock does not need any divider*/
writel(0x100, DSI_BYTE0_CFG_RCGR);
writel(0x1, DSI_BYTE0_CMD_RCGR);
writel(0x1, DSI_BYTE0_CBCR);
/* Configure Pixel clock */
writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
writel(0x1, DSI_PIXEL0_CMD_RCGR);
writel(0x1, DSI_PIXEL0_CBCR);
writel(pclk0_m, DSI_PIXEL0_M);
writel(pclk0_n, DSI_PIXEL0_N);
writel(pclk0_d, DSI_PIXEL0_D);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
ASSERT(0);
}
if (dual_dsi) {
/* Configure Byte 1 clock */
writel(0x100, DSI_BYTE1_CFG_RCGR);
writel(0x1, DSI_BYTE1_CMD_RCGR);
writel(0x1, DSI_BYTE1_CBCR);
/* Configure Pixel clock */
writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
writel(0x1, DSI_PIXEL1_CMD_RCGR);
writel(0x1, DSI_PIXEL1_CBCR);
writel(pclk0_m, DSI_PIXEL1_M);
writel(pclk0_n, DSI_PIXEL1_N);
writel(pclk0_d, DSI_PIXEL1_D);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
ASSERT(0);
}
}
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
char sdc_clk[64];
unsigned rate;
uint32_t reg = 0;
snprintf(sdc_clk, 64, "sdc%u_clk", interface);
switch(freq)
{
case MMC_CLK_400KHZ:
rate = 144000;
break;
case MMC_CLK_48MHZ:
case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
rate = 48000000;
break;
default:
ASSERT(0);
};
clk_get_set_enable(sdc_clk, rate, 1);
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
writel(reg, MMC_BOOT_MCI_CLK);
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
char sdc_clk[64];
unsigned rate;
uint32_t reg = 0;
snprintf(sdc_clk, 64, "sdc%u_clk", interface);
/* Disalbe MCI_CLK before changing the sdcc clock */
mmc_boot_mci_clk_disable();
switch(freq)
{
case MMC_CLK_400KHZ:
rate = 144000;
break;
case MMC_CLK_48MHZ:
case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
rate = 48000000;
break;
case MMC_CLK_96MHZ:
rate = 96000000;
break;
default:
ASSERT(0);
};
clk_get_set_enable(sdc_clk, rate, 1);
/* Enable MCI clk */
mmc_boot_mci_clk_enable();
}
void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
{
uint8_t ret = 0;
char clk_name[64];
struct clk *qup_clk;
snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id);
ret = clk_get_set_enable(clk_name, 0 , 1);
if (ret) {
dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
return;
}
snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id,
(qup_id + 1));
qup_clk = clk_get(clk_name);
if (!qup_clk) {
dprintf(CRITICAL, "Failed to get %s\n", clk_name);
return;
}
ret = clk_enable(qup_clk);
if (ret) {
dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
return;
}
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
int ret;
uint32_t reg;
char clk_name[64];
snprintf(clk_name, 64, "sdc%u_core_clk", interface);
/* Disalbe MCI_CLK before changing the sdcc clock */
#ifndef MMC_SDHCI_SUPPORT
mmc_boot_mci_clk_disable();
#endif
if(freq == MMC_CLK_400KHZ)
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
}
else if(freq == MMC_CLK_96MHZ)
{
ret = clk_get_set_enable(clk_name, 100000000, 1);
}
else if(freq == MMC_CLK_200MHZ)
{
ret = clk_get_set_enable(clk_name, 200000000, 1);
}
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
ASSERT(0);
}
if(ret)
{
dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
ASSERT(0);
}
/* Enalbe MCI clock */
#ifndef MMC_SDHCI_SUPPORT
mmc_boot_mci_clk_enable();
#endif
}
/* Initialize all clocks needed by Display */
void mmss_clock_init(void)
{
int ret;
/* Configure Byte clock */
writel(0x100, DSI_BYTE0_CFG_RCGR);
writel(0x1, DSI_BYTE0_CMD_RCGR);
writel(0x1, DSI_BYTE0_CBCR);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure MMSSNOC AXI clock */
ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure MMSSNOC AXI clock */
ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure AXI clock */
ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure Pixel clock */
writel(0x102, DSI_PIXEL0_CFG_RCGR);
writel(0x1, DSI_PIXEL0_CMD_RCGR);
writel(0x1, DSI_PIXEL0_CBCR);
}
void clock_ce_enable(uint8_t instance)
{
int ret;
char clk_name[64];
snprintf(clk_name, 64, "ce%u_src_clk", instance);
ret = clk_get_set_enable(clk_name, 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
ASSERT(0);
}
snprintf(clk_name, 64, "ce%u_core_clk", instance);
ret = clk_get_set_enable(clk_name, 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
ASSERT(0);
}
snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
ret = clk_get_set_enable(clk_name, 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
ASSERT(0);
}
snprintf(clk_name, 64, "ce%u_axi_clk", instance);
ret = clk_get_set_enable(clk_name, 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Wait for 48 * #pipes cycles.
* This is necessary as immediately after an access control reset (boot up)
* or a debug re-enable, the Crypto core sequentially clears its internal
* pipe key storage memory. If pipe key initialization writes are attempted
* during this time, they may be overwritten by the internal clearing logic.
*/
udelay(1);
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
int ret;
ret = clk_get_set_enable("uart3_iface_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set uart3_iface_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("uart3_core_clk", 7372800, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set uart3_core_clk ret = %d\n", ret);
ASSERT(0);
}
}
/* enables usb30 interface and master clocks */
void clock_usb30_init(void)
{
int ret;
/* interface clock */
ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
ASSERT(0);
}
/* master clock */
ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
ASSERT(0);
}
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
int ret;
uint32_t reg;
char clk_name[64];
snprintf(clk_name, 64, "sdc%u_core_clk", interface);
if(freq == MMC_CLK_400KHZ)
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
}
else
{
dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
ASSERT(0);
}
if(ret)
{
dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
ASSERT(0);
}
reg = 0;
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
writel(reg, MMC_BOOT_MCI_CLK);
/* Wait for the MMC_BOOT_MCI_CLK write to go through. */
mmc_mclk_reg_wr_delay();
/* Wait 1 ms to provide the free running SD CLK to the card. */
mdelay(1);
}
/* Configure clocks for SDCC Calibration circuit */
void clock_config_cdc(uint32_t interface)
{
int ret = 0;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface);
ret = clk_get_set_enable(clk_name, 0 , 1);
if (ret)
{
dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
ASSERT(0);
}
snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface);
ret = clk_get_set_enable(clk_name, 0 , 1);
if (ret)
{
dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
ASSERT(0);
}
}
void clock_bumpup_pipe3_clk()
{
int ret = 0;
ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
ASSERT(0);
}
return;
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
int ret;
char iclk[64];
char cclk[64];
snprintf(iclk, 64, "uart%u_iface_clk", id);
snprintf(cclk, 64, "uart%u_core_clk", id);
ret = clk_get_set_enable(iclk, 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
ASSERT(0);
}
ret = clk_get_set_enable(cclk, 7372800, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
ASSERT(0);
}
}
/* Configure crypto engine clock */
void ce_clock_init(void)
{
uint32_t platform_id;
platform_id = board_platform_id();
if ((platform_id == APQ8064) || (platform_id == APQ8064AA)
|| (platform_id == APQ8064AB))
{
/* Enable HCLK for CE3 */
clk_get_set_enable("ce3_pclk", 0, 1);
/* Enable core clk for CE3 */
clk_get_set_enable("ce3_clk", 0, 1);
}
else
{
/* Enable HCLK for CE1 */
clk_get_set_enable("ce1_pclk", 0, 1);
/* Enable core clk for CE3 */
clk_get_set_enable("ce1_clk", 0, 1);
}
}
void clock_init_mmc(uint32_t interface)
{
char clk_name[64];
int ret;
snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
/* enable interface clock */
ret = clk_get_set_enable(clk_name, 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
ASSERT(0);
}
}
void edp_clk_enable(void)
{
int ret;
/* Configure MMSSNOC AXI clock */
ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure MMSSNOC AXI clock */
ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
ASSERT(0);
}
/* Configure AXI clock */
ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("edp_pixel_clk", 138500000, 1);
if (ret) {
dprintf(CRITICAL, "failed to set edp_pixel_clk ret = %d\n",
ret);
ASSERT(0);
}
ret = clk_get_set_enable("edp_link_clk", 270000000, 1);
if (ret) {
dprintf(CRITICAL, "failed to set edp_link_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("edp_aux_clk", 19200000, 1);
if (ret) {
dprintf(CRITICAL, "failed to set edp_aux_clk ret = %d\n", ret);
ASSERT(0);
}
}
/* enables usb30 clocks */
void clock_usb30_init(void)
{
int ret;
ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
ASSERT(0);
}
ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1);
if(ret)
{
dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
ASSERT(0);
}
}
void hsusb_clock_init(void)
{
clk_get_set_enable("usb_hs_clk", 60000000, 1);
}
