static void __init imx6q_1588_init(void) { struct device_node *np; struct clk *ptp_clk; struct clk *enet_ref; struct regmap *gpr; u32 clksel; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); if (!np) { pr_warn("%s: failed to find fec node\n", __func__); return; } ptp_clk = of_clk_get(np, 2); if (IS_ERR(ptp_clk)) { pr_warn("%s: failed to get ptp clock\n", __func__); goto put_node; } enet_ref = clk_get_sys(NULL, "enet_ref"); if (IS_ERR(enet_ref)) { pr_warn("%s: failed to get enet clock\n", __func__); goto put_ptp_clk; } /* * If enet_ref from ANATOP/CCM is the PTP clock source, we need to * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad * (external OSC), and we need to clear the bit. */ clksel = clk_is_match(ptp_clk, enet_ref) ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : IMX6Q_GPR1_ENET_CLK_SEL_PAD; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, clksel); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); put_node: of_node_put(np); }
/* traverse cpu nodes to get cpu mask of sharing clock wire */ static void set_affected_cpus(struct cpufreq_policy *policy) { struct cpumask *dstp = policy->cpus; struct clk *clk; int i; for_each_present_cpu(i) { clk = cpu_to_clk(i); if (IS_ERR(clk)) { pr_err("%s: no clock for cpu %d\n", __func__, i); continue; } if (clk_is_match(policy->clk, clk)) cpumask_set_cpu(i, dstp); } }
static int kirkwood_i2s_dev_probe(struct platform_device *pdev) { struct kirkwood_asoc_platform_data *data = pdev->dev.platform_data; struct snd_soc_dai_driver *soc_dai = kirkwood_i2s_dai; struct kirkwood_dma_data *priv; struct resource *mem; struct device_node *np = pdev->dev.of_node; int err; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) { dev_err(&pdev->dev, "allocation failed\n"); return -ENOMEM; } dev_set_drvdata(&pdev->dev, priv); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->io = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(priv->io)) return PTR_ERR(priv->io); priv->irq = platform_get_irq(pdev, 0); if (priv->irq <= 0) { dev_err(&pdev->dev, "platform_get_irq failed\n"); return -ENXIO; } if (np) { priv->burst = 128; /* might be 32 or 128 */ } else if (data) { priv->burst = data->burst; } else { dev_err(&pdev->dev, "no DT nor platform data ?!\n"); return -EINVAL; } priv->clk = devm_clk_get(&pdev->dev, np ? "internal" : NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "no clock\n"); return PTR_ERR(priv->clk); } err = clk_prepare_enable(priv->clk); if (err < 0) return err; priv->extclk = devm_clk_get(&pdev->dev, "extclk"); if (IS_ERR(priv->extclk)) { if (PTR_ERR(priv->extclk) == -EPROBE_DEFER) return -EPROBE_DEFER; } else { if (clk_is_match(priv->extclk, priv->clk)) { devm_clk_put(&pdev->dev, priv->extclk); priv->extclk = ERR_PTR(-EINVAL); } else { dev_info(&pdev->dev, "found external clock\n"); clk_prepare_enable(priv->extclk); soc_dai = kirkwood_i2s_dai_extclk; } } /* Some sensible defaults - this reflects the powerup values */ priv->ctl_play = KIRKWOOD_PLAYCTL_SIZE_24; priv->ctl_rec = KIRKWOOD_RECCTL_SIZE_24; /* Select the burst size */ if (priv->burst == 32) { priv->ctl_play |= KIRKWOOD_PLAYCTL_BURST_32; priv->ctl_rec |= KIRKWOOD_RECCTL_BURST_32; } else { priv->ctl_play |= KIRKWOOD_PLAYCTL_BURST_128; priv->ctl_rec |= KIRKWOOD_RECCTL_BURST_128; } err = snd_soc_register_component(&pdev->dev, &kirkwood_i2s_component, soc_dai, 2); if (err) { dev_err(&pdev->dev, "snd_soc_register_component failed\n"); goto err_component; } err = snd_soc_register_platform(&pdev->dev, &kirkwood_soc_platform); if (err) { dev_err(&pdev->dev, "snd_soc_register_platform failed\n"); goto err_platform; } kirkwood_i2s_init(priv); return 0; err_platform: snd_soc_unregister_component(&pdev->dev); err_component: if (!IS_ERR(priv->extclk)) clk_disable_unprepare(priv->extclk); clk_disable_unprepare(priv->clk); return err; }