/* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { /* we'll stick with the crummy u-boot struct for now.*/ /* doing this as an auto since the struct has to be writeable */ struct edp_device_info device_info; void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); tmu_init(&exynos5420_tmu_info); /* Clock Gating all the unused IP's to save power */ clock_gate(); /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); /* * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 * should be 0 according to the datasheet, but has experimentally * been found to come up as 3. This means FIMD SYSMMU is on by * default on Exynos5420. For now we are disabling FIMD SYSMMU. */ writel(0x0, (void *)0x14640000); writel(0x0, (void *)0x14680000); lcd_vdd(); /* Start the fimd running before you do the phy and lcd setup. * why do fimd before training etc? * because we need a data stream from * the fimd or the clock recovery step fails. */ vidinfo.screen_base = fb_addr; exynos_fimd_lcd_init(&vidinfo); parade_dp_bridge_setup(); /* this might get more dynamic in future ... */ memset(&device_info, 0, sizeof(device_info)); device_info.disp_info.name = (char *)"Pit display"; device_info.disp_info.h_total = 1366; device_info.disp_info.v_total = 768; device_info.video_info = dp_video_info; device_info.raw_edid = panel_edid; exynos_init_dp(&device_info); udelay(LCD_T3_DELAY_MS * 1000); backlight_vdd(); backlight_pwm(); backlight_en(); }
/* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { int dp_tries; struct s5p_dp_device dp_device = { .base = exynos_dp1, .video_info = &dp_video_info, }; void *fb_addr = (void *)(get_fb_base_kb() * KiB); prepare_usb(); gpio_init(); setup_storage(); i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE); i2c_init(7, I2C_0_SPEED, I2C_SLAVE); tmu_init(&exynos5250_tmu_info); /* Clock Gating all the unused IP's to save power */ clock_gate(); /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); sdmmc_vdd(); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); // FIXME: should timeout do { udelay(50); } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } if (dp_controller_init(&dp_device)) continue; udelay(LCD_T3_DELAY_MS * 1000); backlight_vdd(); backlight_pwm(); backlight_en(); /* if we're here, we're successful */ break; } if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); setup_usb(); // Uncomment to get excessive GPIO output: // gpio_info(); }
int board_init(void) { struct fdt_memory mem_config; /* Record the time we spent before SPL */ bootstage_add_record(BOOTSTAGE_ID_START_SPL, "spl_start", 0, CONFIG_SPL_TIME_US); bootstage_mark_name(BOOTSTAGE_ID_BOARD_INIT, "board_init"); if (fdtdec_decode_memory(gd->fdt_blob, &mem_config)) { debug("%s: Failed to decode memory\n", __func__); return -1; } gd->bd->bi_boot_params = mem_config.start + 0x100UL; #ifdef CONFIG_OF_CONTROL gd->bd->bi_arch_number = fdtdec_get_config_int(gd->fdt_blob, "machine-arch-id", -1); if (gd->bd->bi_arch_number == -1U) debug("Warning: No /config/machine-arch-id defined in fdt\n"); #endif #ifdef CONFIG_EXYNOS_SPI spi_init(); #endif if (board_i2c_arb_init(gd->fdt_blob)) return -1; board_i2c_init(gd->fdt_blob); #ifdef CONFIG_TPS65090_POWER tps65090_init(); /* * If we just reset, disable the backlight and lcd fets before * [re-]initializing the lcd. This ensures we are always in the same * state during lcd init. We've seen some oddities with these fets, so * this removes a bit of uncertainty. */ if (board_is_processor_reset()) { tps65090_fet_disable(1); tps65090_fet_disable(6); } #endif exynos_lcd_check_next_stage(gd->fdt_blob, 0); if (max77686_enable_32khz_cp()) { debug("%s: Failed to enable max77686 32khz coprocessor clock\n", __func__); return -1; } #if defined CONFIG_EXYNOS_CPUFREQ if (exynos5250_cpufreq_init(gd->fdt_blob)) { debug("%s: Failed to init CPU frequency scaling\n", __func__); return -1; } #endif #if defined CONFIG_EXYNOS_TMU if (tmu_init(gd->fdt_blob)) { debug("%s: Failed to init TMU\n", __func__); return -1; } #endif /* Clock Gating all the unused IP's to save power */ clock_gate(); /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); if (board_init_mkbp_devices(gd->fdt_blob)) return -1; board_configure_analogix(); board_enable_audio_codec(); exynos_lcd_check_next_stage(gd->fdt_blob, 0); bootstage_mark_name(BOOTSTAGE_ID_BOARD_INIT_DONE, "board_init_done"); return 0; }
/* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { int dp_tries; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &dp_video_info, }; void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE); i2c_init(7, I2C_0_SPEED, I2C_SLAVE); tmu_init(&exynos5250_tmu_info); /* Clock Gating all the unused IP's to save power */ clock_gate(); /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); // FIXME: should timeout do { udelay(50); } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } if (dp_controller_init(&dp_device)) continue; udelay(LCD_T3_DELAY_MS * 1000); backlight_vdd(); backlight_pwm(); backlight_en(); /* if we're here, we're successful */ break; } if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); // Uncomment to get excessive GPIO output: // gpio_info(); } static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ exynos5250_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_invalidate_all(); dcache_mmu_enable(); /* this is going to move, but we must have it now and we're * not sure where */ exception_init(); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; const unsigned lr_frame_size = 256; clock_epll_set_rate(epll_hz); clock_select_i2s_clk_source(); clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); power_enable_xclkout(); }