void clock_early_init(void)
{
/*
* PLLP output frequency set to 216MHz
* PLLC output frequency set to 600Mhz
*
* TODO: Can we calculate these values instead of hard-coding?
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
break;
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
break;
case CLOCK_OSC_FREQ_19_2:
default:
/*
* These are not supported. It is too early to print a
* message and the UART likely won't work anyway due to the
* oscillator being wrong.
*/
break;
}
}
int board_usb_init(const void *blob)
{
struct fdt_usb config;
unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
enum clock_osc_freq freq;
int node_list[USB_PORTS_MAX];
int node, count, i;
/* Set up the USB clocks correctly based on our oscillator frequency */
freq = clock_get_osc_freq();
config_clock(usb_pll[freq]);
/* count may return <0 on error */
count = fdtdec_find_aliases_for_id(blob, "usb",
COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
for (i = 0; i < count; i++) {
debug("USB %d: ", i);
node = node_list[i];
if (!node)
continue;
if (fdt_decode_usb(blob, node, osc_freq, &config)) {
debug("Cannot decode USB node %s\n",
fdt_get_name(blob, node, NULL));
return -1;
}
if (add_port(&config, usb_pll[freq]))
return -1;
set_host_mode(&config);
}
return 0;
}
static const unsigned *get_pll_timing(struct fdt_usb_controller *controller)
{
const unsigned *timing;
timing = controller->pll_parameter +
clock_get_osc_freq() * PARAM_COUNT;
return timing;
}
static const unsigned *get_pll_timing(void)
{
const unsigned *timing;
timing = controller->pll_parameter +
clock_get_osc_freq() * PARAM_COUNT;
return timing;
}
int board_usb_init(const void *blob)
{
struct fdt_usb config;
enum clock_osc_freq freq;
int node_list[USB_PORTS_MAX];
int node, count, i;
/* Set up the USB clocks correctly based on our oscillator frequency */
freq = clock_get_osc_freq();
config_clock(usb_pll[freq]);
/* count may return <0 on error */
count = fdtdec_find_aliases_for_id(blob, "usb",
COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
for (i = 0; i < count; i++) {
if (port_count == USB_PORTS_MAX) {
printf("tegrausb: Cannot register more than %d ports\n",
USB_PORTS_MAX);
return -1;
}
debug("USB %d: ", i);
node = node_list[i];
if (!node)
continue;
if (fdt_decode_usb(blob, node, &config)) {
debug("Cannot decode USB node %s\n",
fdt_get_name(blob, node, NULL));
return -1;
}
config.initialized = 0;
/* add new USB port to the list of available ports */
port[port_count++] = config;
}
return 0;
}
/* set up the UTMI USB controller with the parameters provided */
static int init_utmi_usb_controller(struct fdt_usb *config)
{
u32 val;
int loop_count;
const unsigned *timing;
struct usb_ctlr *usbctlr = config->reg;
clock_enable(config->periph_id);
/* Reset the usb controller */
usbf_reset_controller(config, usbctlr);
/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Follow the crystal clock disable by >100ns delay */
udelay(1);
/*
* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
* mux must be switched to actually use a_sess_vld threshold.
*/
if (fdt_gpio_isvalid(&config->vbus_gpio)) {
clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
VBUS_SENSE_CTL_MASK,
VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
}
/*
* PLL Delay CONFIGURATION settings. The following parameters control
* the bring up of the plls.
*/
timing = usb_pll[clock_get_osc_freq()];
val = readl(&usbctlr->utmip_misc_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &usbctlr->utmip_misc_cfg1);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&usbctlr->utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &usbctlr->utmip_pll_cfg1);
/* Setting the tracking length time */
clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
UTMIP_BIAS_PDTRK_COUNT_MASK,
timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
/* Program debounce time for VBUS to become valid */
clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
UTMIP_DEBOUNCE_CFG0_MASK,
timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
/* Disable battery charge enabling bit */
setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
/*
* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
* Setting these fields, together with default values of the
* other fields, results in programming the registers below as
* follows:
* UTMIP_HSRX_CFG0 = 0x9168c000
* UTMIP_HSRX_CFG1 = 0x13
*/
/* Set PLL enable delay count and Crystal frequency count */
val = readl(&usbctlr->utmip_hsrx_cfg0);
clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
writel(val, &usbctlr->utmip_hsrx_cfg0);
/* Configure the UTMIP_HS_SYNC_START_DLY */
clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
UTMIP_HS_SYNC_START_DLY_MASK,
utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
/* Preceed the crystal clock disable by >100ns delay. */
udelay(1);
/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Finished the per-controller init. */
/* De-assert UTMIP_RESET to bring out of reset. */
clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
/* Wait for the phy clock to become valid in 100 ms */
for (loop_count = 100000; loop_count != 0; loop_count--) {
if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
break;
udelay(1);
}
if (!loop_count)
return -1;
/* Disable ICUSB FS/LS transceiver */
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
return 0;
}
int board_usb_init(const void *blob)
{
#ifdef CONFIG_OF_CONTROL
struct fdt_usb config;
int clk_done = 0;
int node, upto = 0;
unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
#if defined(CONFIG_TEGRA3)
struct usb_ctlr *usb1ctlr;
#endif
do {
node = fdt_decode_next_alias(blob, "usb",
COMPAT_NVIDIA_TEGRA250_USB, &upto);
if (node < 0)
break;
if (fdt_decode_usb(blob, node, osc_freq, &config))
return -1;
if (!config.enabled)
continue;
/* The first port we find gets to set the clocks */
if (!clk_done) {
config_clock(config.params);
clk_done = 1;
}
if (config.host_mode) {
/* Only one host-dev port is supported */
if (host_dev_ctlr)
return -1;
host_dev_ctlr = config.reg;
}
if (add_port(config.periph_id, config.reg, config.params,
config.utmi))
return -1;
#if defined(CONFIG_TEGRA3)
fdt_setup_gpio(&config.vbus_gpio);
fdt_setup_gpio(&config.vbus_pullup_gpio);
usb1ctlr = (struct usb_ctlr *)NV_PA_USB1_BASE;
/*
* BIAS Pad Power Down is common among all 3 USB
* controllers and can be controlled from USB1 only.
*/
bf_writel(UTMIP_BIASPD, 0, &usb1ctlr->utmip_bias_cfg0);
#endif
} while (node);
#else
enum clock_osc_freq freq;
const int *params;
/* Get the Oscillator frequency */
freq = clock_get_osc_freq();
/* Enable PLL U for USB */
params = &usb_pll[freq][0];
config_clock(params);
/* Set up our two ports */
#ifdef CONFIG_TEGRA2_USB1_HOST
host_dev_ctlr = (struct usb_ctlr *)NV_PA_USB1_BASE;
#endif
probe_port((struct usb_ctlr *)CONFIG_TEGRA2_USB0, params);
probe_port((struct usb_ctlr *)CONFIG_TEGRA2_USB1, params);
#endif /* CONFIG_OF_CONTROL */
usb_set_host_mode();
port_current = -1;
return 0;
}
