static int __init init_hrt_clocksource(void)
{
if (!scx200_cb_present())
return -ENODEV;
if (!request_region(scx200_cb_base + SCx200_TIMER_OFFSET,
SCx200_TIMER_SIZE,
"NatSemi SCx200 High-Resolution Timer")) {
printk(KERN_WARNING NAME ": unable to lock timer region\n");
return -ENODEV;
}
outb(HR_TMEN | (mhz27 ? HR_TMCLKSEL : 0),
scx200_cb_base + SCx200_TMCNFG_OFFSET);
if (mhz27) {
cs_hrt.shift = HRT_SHIFT_27;
cs_hrt.mult = clocksource_hz2mult((HRT_FREQ + ppm) * 27,
cs_hrt.shift);
} else {
cs_hrt.shift = HRT_SHIFT_1;
cs_hrt.mult = clocksource_hz2mult(HRT_FREQ + ppm,
cs_hrt.shift);
}
printk(KERN_INFO "enabling scx200 high-res timer (%s MHz +%d ppm)\n",
mhz27 ? "27":"1", ppm);
return clocksource_register(&cs_hrt);
}
static int __init init_hrt_clocksource(void)
{
/* Make sure scx200 has initialized the configuration block */
if (!scx200_cb_present())
return -ENODEV;
/* Reserve the timer's ISA io-region for ourselves */
if (!request_region(scx200_cb_base + SCx200_TIMER_OFFSET,
SCx200_TIMER_SIZE,
"NatSemi SCx200 High-Resolution Timer")) {
;
return -ENODEV;
}
/* write timer config */
outb(HR_TMEN | (mhz27 ? HR_TMCLKSEL : 0),
scx200_cb_base + SCx200_TMCNFG_OFFSET);
if (mhz27) {
cs_hrt.shift = HRT_SHIFT_27;
cs_hrt.mult = clocksource_hz2mult((HRT_FREQ + ppm) * 27,
cs_hrt.shift);
} else {
cs_hrt.shift = HRT_SHIFT_1;
cs_hrt.mult = clocksource_hz2mult(HRT_FREQ + ppm,
cs_hrt.shift);
}
// printk(KERN_INFO "enabling scx200 high-res timer (%s MHz +%d ppm)\n",
;
return clocksource_register(&cs_hrt);
}
/*
* Called very early from setup_arch() to set cycles_per_sec.
* We initialize it early so we can use it to set up loops_per_jiffy.
*/
void __init setup_clock(void)
{
cycles_per_sec = hv_sysconf(HV_SYSCONF_CPU_SPEED);
sched_clock_mult =
clocksource_hz2mult(cycles_per_sec, SCHED_CLOCK_SHIFT);
cycle_counter_cs.mult =
clocksource_hz2mult(cycles_per_sec, cycle_counter_cs.shift);
}
static void __init cns3xxx_clocksource_init(void)
{
timer4_cs.mult = clocksource_hz2mult(100 * KHZ, timer4_cs.shift);
timer2_cs.mult = clocksource_hz2mult(1 * KHZ, timer2_cs.shift);
timer1_cs.mult = clocksource_hz2mult((CNS3XXX_PCLK * MHZ), timer1_cs.shift);
clocksource_register(&timer4_cs);
clocksource_register(&timer2_cs);
clocksource_register(&timer1_cs);
}
static void __init init_sh_clocksource(void)
{
if (!sh_hpt_frequency || clocksource_sh.read == null_hpt_read)
return;
clocksource_sh.mult = clocksource_hz2mult(sh_hpt_frequency,
clocksource_sh.shift);
timer_ticks_per_nsec_quotient =
clocksource_hz2mult(sh_hpt_frequency, NSEC_PER_CYC_SHIFT);
clocksource_register(&clocksource_sh);
}
static int __init omap_init_clocksource_32k(void)
{
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
struct clk *sync_32k_ick;
if (cpu_is_omap16xx())
clocksource_32k.read = omap16xx_32k_read;
else if (cpu_is_omap2420())
clocksource_32k.read = omap2420_32k_read;
else if (cpu_is_omap2430())
clocksource_32k.read = omap2430_32k_read;
else if (cpu_is_omap34xx())
clocksource_32k.read = omap34xx_32k_read;
else if (cpu_is_omap44xx())
clocksource_32k.read = omap44xx_32k_read;
else
return -ENODEV;
sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
if (sync_32k_ick)
clk_enable(sync_32k_ick);
clocksource_32k.mult = clocksource_hz2mult(32768,
clocksource_32k.shift);
if (clocksource_register(&clocksource_32k))
printk(err, clocksource_32k.name);
}
return 0;
}
static void __init pxa_timer_init(void)
{
unsigned long clock_tick_rate;
OIER = 0;
OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
if (cpu_is_pxa21x() || cpu_is_pxa25x())
clock_tick_rate = 3686400;
else if (machine_is_mainstone())
clock_tick_rate = 3249600;
else
clock_tick_rate = 3250000;
set_oscr2ns_scale(clock_tick_rate);
ckevt_pxa_osmr0.mult =
div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
ckevt_pxa_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
ckevt_pxa_osmr0.min_delta_ns =
clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
cksrc_pxa_oscr0.mult =
clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
setup_irq(IRQ_OST0, &pxa_ost0_irq);
clocksource_register(&cksrc_pxa_oscr0);
clockevents_register_device(&ckevt_pxa_osmr0);
}
void __init time_init(void)
{
unsigned int year, mon, day, hour, min, sec;
extern void arch_gettod(int *year, int *mon, int *day, int *hour,
int *min, int *sec);
unsigned ctrl;
arch_gettod(&year, &mon, &day, &hour, &min, &sec);
if ((year += 1900) < 1970)
year += 100;
xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
xtime.tv_nsec = 0;
wall_to_monotonic.tv_sec = -xtime.tv_sec;
timer_membase = (unsigned long)ioremap((unsigned long)na_timer0, 32);
setup_irq(na_timer0_irq, &nios2_timer_irq);
write_timerperiod(NIOS2_TIMER_PERIOD - 1);
/* clocksource initialize */
nios2_timer.mult =
clocksource_hz2mult(nasys_clock_freq, nios2_timer.shift);
clocksource_register(&nios2_timer);
/* interrupt enable + continuous + start */
ctrl =
ALTERA_TIMER_CONTROL_ITO_MSK | ALTERA_TIMER_CONTROL_CONT_MSK |
ALTERA_TIMER_CONTROL_START_MSK;
outw(ctrl, timer_membase + ALTERA_TIMER_CONTROL_REG);
}
void hw_timer_init(void)
{
setup_irq(mcf_timervector, &mcftmr_timer_irq);
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
mcftmr_cycles_per_jiffy = FREQ / HZ;
/*
* The coldfire timer runs from 0 to TRR included, then 0
* again and so on. It counts thus actually TRR + 1 steps
* for 1 tick, not TRR. So if you want n cycles,
* initialize TRR with n - 1.
*/
__raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
clocksource_register(&mcftmr_clk);
mcf_settimericr(1, mcf_timerlevel);
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
}
static int __init init_acpi_pm_clocksource(void)
{
u32 value1, value2;
unsigned int i;
if (!pmtmr_ioport)
return -ENODEV;
clocksource_acpi_pm.mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC,
clocksource_acpi_pm.shift);
/* "verify" this timing source: */
value1 = read_pmtmr();
for (i = 0; i < 10000; i++) {
value2 = read_pmtmr();
if (value2 == value1)
continue;
if (value2 > value1)
goto pm_good;
if ((value2 < value1) && ((value2) < 0xFFF))
goto pm_good;
printk(KERN_INFO "PM-Timer had inconsistent results:"
" 0x%#x, 0x%#x - aborting.\n", value1, value2);
return -EINVAL;
}
printk(KERN_INFO "PM-Timer had no reasonable result:"
" 0x%#x - aborting.\n", value1);
return -ENODEV;
pm_good:
if (verify_pmtmr_rate() != 0)
return -ENODEV;
return clocksource_register(&clocksource_acpi_pm);
}
static void __init pxa_timer_init(void)
{
unsigned long clock_tick_rate = get_clock_tick_rate();
OIER = 0;
OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
set_oscr2ns_scale(clock_tick_rate);
ckevt_pxa_osmr0.mult =
div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
ckevt_pxa_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
ckevt_pxa_osmr0.min_delta_ns =
clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
ckevt_pxa_osmr0.cpumask = cpumask_of(0);
cksrc_pxa_oscr0.mult =
clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
setup_irq(IRQ_OST0, &pxa_ost0_irq);
clocksource_register(&cksrc_pxa_oscr0);
clockevents_register_device(&ckevt_pxa_osmr0);
}
static bool_t virt_cs_init(struct clocksource_t * cs)
{
u64_t rate = arm64_timer_frequecy();
cs->mult = clocksource_hz2mult(rate, cs->shift);
arm64_timer_start();
return TRUE;
}
static void __init msm_timer_init(void)
{
int i;
int res;
for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
struct msm_clock *clock = &msm_clocks[i];
struct clock_event_device *ce = &clock->clockevent;
struct clocksource *cs = &clock->clocksource;
writel(0, clock->regbase + TIMER_ENABLE);
writel(0, clock->regbase + TIMER_CLEAR);
writel(~0, clock->regbase + TIMER_MATCH_VAL);
ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
/* allow at least 10 seconds to notice that the timer wrapped */
ce->max_delta_ns =
clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
/* 4 gets rounded down to 3 */
ce->min_delta_ns = clockevent_delta2ns(4, ce);
ce->cpumask = cpumask_of_cpu(0);
cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
res = clocksource_register(cs);
if (res)
printk(KERN_ERR "msm_timer_init: clocksource_register "
"failed for %s\n", cs->name);
res = setup_irq(clock->irq.irq, &clock->irq);
if (res)
printk(KERN_ERR "msm_timer_init: setup_irq "
"failed for %s\n", cs->name);
clockevents_register_device(ce);
}
}
static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
char *name, unsigned long rating)
{
struct clocksource *cs = &p->cs;
cs->name = name;
cs->rating = rating;
cs->read = sh_cmt_clocksource_read;
cs->enable = sh_cmt_clocksource_enable;
cs->disable = sh_cmt_clocksource_disable;
cs->suspend = sh_cmt_clocksource_disable;
cs->resume = sh_cmt_clocksource_resume;
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
/* clk_get_rate() needs an enabled clock */
clk_enable(p->clk);
p->rate = clk_get_rate(p->clk) / ((p->width == 16) ? 512 : 8);
clk_disable(p->clk);
/* TODO: calculate good shift from rate and counter bit width */
cs->shift = 0;
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
dev_info(&p->pdev->dev, "used as clock source\n");
clocksource_register(cs);
return 0;
}
void __cpuinit jz_clocksource_init(void)
{
struct clk *ext_clk = clk_get(NULL, "ext1");
tmr_src.cs.mult =
clocksource_hz2mult(clk_get_rate(ext_clk) / CLKSOURCE_DIV,
tmr_src.cs.shift);
clk_put(ext_clk);
clocksource_register(&tmr_src.cs);
tmr_src.clk_gate = clk_get(NULL, "tcu");
if (IS_ERR(tmr_src.clk_gate)) {
tmr_src.clk_gate = NULL;
printk("warning: tcu clk get fail!\n");
}
if (tmr_src.clk_gate)
clk_enable(tmr_src.clk_gate);
tmr_src.channel = CLKSOURCE_CH;
tcu_writel(TCU_TSCR, 1 << CLKSOURCE_CH);
apbost_writel(OST_CNTL, 0);
apbost_writel(OST_CNTH, 0);
apbost_writel(OST_DR, 0);
tcu_writel(TCU_TFCR, TFR_OSTF);
tcu_writel(TCU_TMSR, TMR_OSTM);
apbost_writel(OST_CSR, OSTCSR_CNT_MD |
CSRDIV(CLKSOURCE_DIV) | CSR_EXT_EN); // 16 prescale ext clk
}
static void __init pxa_timer_init(void)
{
struct timespec tv;
unsigned long flags;
set_rtc = pxa_set_rtc;
tv.tv_nsec = 0;
tv.tv_sec = pxa_get_rtc_time();
do_settimeofday(&tv);
OIER = 0; /* disable any timer interrupts */
OSSR = 0xf; /* clear status on all timers */
setup_irq(IRQ_OST0, &pxa_timer_irq);
local_irq_save(flags);
OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
OSMR0 = OSCR + LATCH; /* set initial match */
local_irq_restore(flags);
/*
* OSCR runs continuously on PXA and is not written to,
* so we can use it as clock source directly.
*/
clocksource_pxa.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_pxa.shift);
clocksource_register(&clocksource_pxa);
}
static void __init gptimer_clocksource_init(void)
{
clksrc_gptimer.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
clksrc_gptimer.shift);
clocksource_register(&clksrc_gptimer);
return;
}
int __weak avr32_hpt_init(void)
{
int ret;
unsigned long mult, shift, count_hz;
count_hz = clk_get_rate(boot_cpu_data.clk);
shift = clocksource_avr32.shift;
mult = clocksource_hz2mult(count_hz, shift);
clocksource_avr32.mult = mult;
{
u64 tmp;
tmp = TICK_NSEC;
tmp <<= shift;
tmp += mult / 2;
do_div(tmp, mult);
cycles_per_jiffy = tmp;
}
ret = setup_irq(0, &timer_irqaction);
if (ret) {
pr_debug("timer: could not request IRQ 0: %d\n", ret);
return -ENODEV;
}
printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
"%lu.%03lu MHz\n",
((count_hz + 500) / 1000) / 1000,
((count_hz + 500) / 1000) % 1000);
return 0;
}
void __init orion_time_init(unsigned int irq, unsigned int tclk)
{
u32 u;
ticks_per_jiffy = (tclk + HZ/2) / HZ;
/*
* Set scale and timer for sched_clock
*/
setup_sched_clock(tclk);
/*
* Setup free-running clocksource timer (interrupts
* disabled.)
*/
writel(0xffffffff, TIMER0_VAL);
writel(0xffffffff, TIMER0_RELOAD);
u = readl(BRIDGE_MASK);
writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
u = readl(TIMER_CTRL);
writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
clocksource_register(&orion_clksrc);
/*
* Setup clockevent timer (interrupt-driven.)
*/
setup_irq(irq, &orion_timer_irq);
orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
orion_clkevt.cpumask = cpumask_of(0);
clockevents_register_device(&orion_clkevt);
}
static inline void setup_clksrc(u32 freq)
{
struct clocksource *cs = &gpt_clocksource;
struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID);
struct timecounter *mt_timecounter;
u64 start_count;
pr_alert("setup_clksrc1: dev->base_addr=0x%lx GPT2_CON=0x%x\n",
(unsigned long)dev->base_addr, __raw_readl(dev->base_addr));
cs->mult = clocksource_hz2mult(freq, cs->shift);
sched_clock_register(mt_read_sched_clock, 32, freq);
setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
0, NULL, 0);
clocksource_register(cs);
start_count = mt_read_sched_clock();
mt_cyclecounter.mult = cs->mult;
mt_cyclecounter.shift = cs->shift;
mt_timecounter = arch_timer_get_timecounter();
timecounter_init(mt_timecounter, &mt_cyclecounter, start_count);
pr_alert("setup_clksrc1: mt_cyclecounter.mult=0x%x mt_cyclecounter.shift=0x%x\n",
mt_cyclecounter.mult, mt_cyclecounter.shift);
pr_alert("setup_clksrc2: dev->base_addr=0x%lx GPT2_CON=0x%x\n",
(unsigned long)dev->base_addr, __raw_readl(dev->base_addr));
}
/*
* ST (system timer) module supports both clockevents and clocksource.
*/
void __init at91rm9200_timer_init(void)
{
/* Disable all timer interrupts, and clear any pending ones */
at91_sys_write(AT91_ST_IDR,
AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
(void) at91_sys_read(AT91_ST_SR);
/* Make IRQs happen for the system timer */
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
*/
at91_sys_write(AT91_ST_RTMR, 1);
/* Setup timer clockevent, with minimum of two ticks (important!!) */
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
clkevt.cpumask = cpumask_of(0);
clockevents_register_device(&clkevt);
/* register clocksource */
clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
clocksource_register(&clk32k);
}
static void __init nios2_time_init(struct device_node *timer)
{
int irq;
unsigned int ctrl;
timer_membase = of_iomap(timer, 0);
if (!timer_membase)
panic("Unable to map timer resource\n");
if (of_property_read_u32(timer, "clock-frequency", &timer_freq))
panic("Unable to get timer clock frequency\n");
irq = irq_of_parse_and_map(timer, 0);
if (irq < 0)
panic("Unable to parse timer irq\n");
if (setup_irq(irq, &nios2_timer_irq))
panic("Unable to setup timer irq\n");
write_timerperiod(NIOS2_TIMER_PERIOD - 1);
/* clocksource initialize */
nios2_timer.mult = clocksource_hz2mult(timer_freq, nios2_timer.shift);
clocksource_register(&nios2_timer);
/* interrupt enable + continuous + start */
ctrl = ALTERA_TIMER_CONTROL_ITO_MSK | ALTERA_TIMER_CONTROL_CONT_MSK |
ALTERA_TIMER_CONTROL_START_MSK;
outw(ctrl, timer_membase + ALTERA_TIMER_CONTROL_REG);
}
static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
char *name, unsigned long rating)
{
struct clocksource *cs = &p->cs;
cs->name = name;
cs->rating = rating;
cs->read = sh_tmu_clocksource_read;
cs->enable = sh_tmu_clocksource_enable;
cs->disable = sh_tmu_clocksource_disable;
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
/* clk_get_rate() needs an enabled clock */
clk_enable(p->clk);
/* channel will be configured at parent clock / 4 */
p->rate = clk_get_rate(p->clk) / 4;
clk_disable(p->clk);
/* TODO: calculate good shift from rate and counter bit width */
cs->shift = 10;
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
dev_info(&p->pdev->dev, "used as clock source\n");
clocksource_register(cs);
return 0;
}
void hw_timer_init(void)
{
int i;
struct clock_event_device *cevent;
writeb(CONFIG_DJ_COUNTER_DIV & DJIO_A_TIMER_COUNTER_DIV_MASK,
DJIO_A_TIMER + DJIO_A_TIMER_COUNTER_DIV);
clocksource_register(&dj_timer_clk);
dj_timer_clk.mult = clocksource_hz2mult(DJ_COUNTER_FREQ,
dj_timer_clk.shift);
cevent = &dj_timera_clock_event; /* Until we need more than 1 */
for (i = 0; i < 1; i++) { /* Until we need more than 1 */
cevent->cpumask = cpumask_of(smp_processor_id());
cevent->mult = div_sc(DJ_COUNTER_FREQ,
NSEC_PER_SEC, cevent->shift);
cevent->max_delta_ns = clockevent_delta2ns(0xFFFF, cevent);
cevent->min_delta_ns = DJ_TIMER_MIN_DELTA_NS;
dj_timer_init(CLOCK_EVT_MODE_UNUSED, cevent);
setup_irq(cevent->irq, &(dj_timer_irqs[i]));
clockevents_register_device(cevent);
}
}
void __init aw_clksrc_init(void)
{
pr_info("%s(%d)\n", __func__, __LINE__);
#if 0 /* start counting on booting, so cannot clear it, otherwise systime will be err */
/* we use 64bits counter as HPET(High Precision Event Timer) */
writel(0, SW_HSTMR_CTRL_REG);
/* config clock source for 64bits counter */
temp = readl(SW_HSTMR_CTRL_REG);
temp &= ~(1<<2);
/* clear 64bits counter */
temp |= (1<<0);
writel(temp, SW_HSTMR_CTRL_REG);
/* wait clear complete */
while(cnt-- && (readl(SW_HSTMR_CTRL_REG) & (1<<0)));
if(unlikely(0 == cnt))
pr_err("%s(%d): wait cleared timeout\n", __func__, __LINE__);
#endif
/* calculate the mult by shift */
aw_clocksrc.mult = clocksource_hz2mult(AW_HPET_CLOCK_SOURCE_HZ, aw_clocksrc.shift);
/* register clock source */
clocksource_register(&aw_clocksrc);
/* set sched clock */
setup_sched_clock(sched_clock_read, 32, AW_HPET_CLOCK_SOURCE_HZ);
pr_info("%s(%d)\n", __func__, __LINE__);
}
/*
* Set up both clocksource and clockevent support.
*/
static void __init at91sam926x_pit_init(void)
{
unsigned long pit_rate;
unsigned bits;
printk (KERN_ALERT "petworm: pit init.\n");
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
/* Initialize and enable the timer */
at91sam926x_pit_reset();
/*
* Register clocksource. The high order bits of PIV are unused,
* so this isn't a 32-bit counter unless we get clockevent irqs.
*/
pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
pit_clk.mask = CLOCKSOURCE_MASK(bits);
clocksource_register(&pit_clk);
/* Set up irq handler */
setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
/* Set up and register clockevents */
pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
clockevents_register_device(&pit_clkevt);
}
static void __init ixp4xx_clocksource_init(void)
{
clocksource_ixp4xx.mult =
clocksource_hz2mult(ixp4xx_timer_freq,
clocksource_ixp4xx.shift);
clocksource_register(&clocksource_ixp4xx);
}
int __init init_mfgpt_clocksource(void)
{
if (num_possible_cpus() > 1) /* MFGPT does not scale! */
return 0;
clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
return clocksource_register(&clocksource_mfgpt);
}
static int __init imx_clocksource_init(void)
{
clocksource_imx.mult =
clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
clocksource_register(&clocksource_imx);
return 0;
}
static int clocksource_init (void)
{
cs.mult = clocksource_hz2mult(1000 * 1000 * 1000, cs.shift);
init_clock(&cs);
return 0;
}