int rcc_osc_ready_int_flag(osc_t osc)
{
switch (osc) {
case PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case PLL2:
return ((RCC_CIR & RCC_CIR_PLL2RDYF) != 0);
break;
case PLL3:
return ((RCC_CIR & RCC_CIR_PLL3RDYF) != 0);
break;
case HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
cm3_assert_not_reached();
}
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32 = 0;
uint8_t i = 0;
bool stepup = false, stepdn = false;
if (length == 0) {
ADC_CHSELR(adc) = 0;
return;
}
reg32 |= (1 << channel[0]);
for (i = 1; i < length; i++) {
reg32 |= (1 << channel[i]);
stepup |= channel[i-1] < channel[i];
stepdn |= channel[i-1] > channel[i];
}
/* Check, if the channel list is in order */
if (stepup && stepdn) {
cm3_assert_not_reached();
}
/* Update the scan direction flag */
if (stepdn) {
ADC_CFGR1(adc) |= ADC_CFGR1_SCANDIR;
} else {
ADC_CFGR1(adc) &= ~ADC_CFGR1_SCANDIR;
}
ADC_CHSELR(adc) = reg32;
}
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case HSI14:
return (RCC_CIR & RCC_CIR_HSI14RDYF) != 0;
break;
case HSI:
return (RCC_CIR & RCC_CIR_HSIRDYF) != 0;
break;
case HSE:
return (RCC_CIR & RCC_CIR_HSERDYF) != 0;
break;
case PLL:
return (RCC_CIR & RCC_CIR_PLLRDYF) != 0;
break;
case LSE:
return (RCC_CIR & RCC_CIR_LSERDYF) != 0;
break;
case LSI:
return (RCC_CIR & RCC_CIR_LSIRDYF) != 0;
break;
}
cm3_assert_not_reached();
}
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
break;
case RCC_HSE:
return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
break;
case RCC_HSI16:
return ((RCC_CIFR & RCC_CIFR_HSIRDYF) != 0);
break;
case RCC_MSI:
return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
break;
case RCC_LSE:
return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
break;
case RCC_LSI:
return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
break;
}
cm3_assert_not_reached();
}
enum rcc_osc rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
switch (RCC_CFGR & RCC_CFGR_SWS) {
case RCC_CFGR_SWS_HSI:
return HSI;
case RCC_CFGR_SWS_HSE:
return HSE;
case RCC_CFGR_SWS_PLL:
return PLL;
}
cm3_assert_not_reached();
}
