void
iic_attach(struct device *parent, struct device *self, void *aux)
{
struct iic_softc *sc = (void *) self;
struct i2cbus_attach_args *iba = aux;
sc->sc_tag = iba->iba_tag;
#if NIPMI > 0
extern int ipmi_enabled;
if (ipmi_enabled) {
printf(": disabled to avoid ipmi0 interactions\n");
return;
}
#endif
printf("\n");
/*
* Attach all i2c devices described in the kernel
* configuration file.
*/
config_search(iic_search, self, NULL);
/*
* Scan for known device signatures.
*/
if (iba->iba_bus_scan)
(iba->iba_bus_scan)(self, aux, iba->iba_bus_scan_arg);
else
iic_scan(self, aux);
}
/*
* The common attach routine:
* Calls the scan routine to search for uba devices.
*/
void
uba_attach(struct uba_softc *sc, paddr_t iopagephys)
{
/*
* Set last free interrupt vector for devices with
* programmable interrupt vectors. Use is to decrement
* this number and use result as interrupt vector.
*/
sc->uh_lastiv = 0x200;
SIMPLEQ_INIT(&sc->uh_resq);
SIMPLEQ_INIT(&sc->uh_resetq);
/*
* Allocate place for unibus I/O space in virtual space.
*/
if (bus_space_map(sc->uh_iot, iopagephys, UBAIOSIZE, 0, &sc->uh_ioh))
return;
if (sc->uh_beforescan)
(*sc->uh_beforescan)(sc);
/*
* Now start searching for devices.
*/
config_search((cfmatch_t)ubasearch,(struct device *)sc, NULL);
if (sc->uh_afterscan)
(*sc->uh_afterscan)(sc);
}
const char *config_batchsize()
{
char *batchfilename;
char *batchsizestr;
unsigned batchsize;
if (batchsize_buf[0] == '\0')
{
batchfilename=config_search("batchsize");
batchsizestr=config_read1l(batchfilename);
free(batchfilename);
batchsize=100;
if (batchsizestr)
{
batchsize=atoi(batchsizestr);
free(batchsizestr);
if (batchsize == 0) batchsize=100;
/* stupid user */
}
if (batchsize <= 0) batchsize=5;
sprintf(batchsize_buf, "%u", batchsize);
}
return (batchsize_buf);
}
void
mainbusattach(struct device *parent, struct device *self, void *aux)
{
printf("\n");
config_search(mainbussearch, self, aux);
}
void
cortexattach(struct device *parent, struct device *self, void *aux)
{
printf("\n");
config_search(cortexsearch, self, aux);
}
void
lrcattach(struct device *parent, struct device *self, void *aux)
{
struct confargs *ca = aux;
struct lrcsoftc *sc = (struct lrcsoftc *)self;
sc->sc_paddr = ca->ca_paddr;
sc->sc_vaddr = IIOV(sc->sc_paddr);
sys_lrc = sc->sc_regs = (struct lrcreg *)sc->sc_vaddr;
printf("\n");
/* sync serial clock with DUART */
sc->sc_regs->lrc_gcr &= ~GCR_SCFREQ;
/* disable VSB */
sc->sc_regs->lrc_bcr &= ~(BCR_VA24 | BCR_VSBEN | BCR_ROEN);
/* set up vector base */
sc->sc_regs->lrc_icr1 = LRC_VECBASE;
/* enable interrupts */
sc->sc_regs->lrc_icr0 = ICR0_GIE;
sc->sc_abortih.ih_fn = lrcabort;
sc->sc_abortih.ih_ipl = IPL_HIGH;
sc->sc_abortih.ih_wantframe = 1;
lrcintr_establish(LRCVEC_ABORT, &sc->sc_abortih, self->dv_xname);
config_search(lrcscan, self, aux);
}
void
ssspi_attach(struct device *parent, struct device *self, void *aux)
{
struct ssspi_softc *sc = (struct ssspi_softc*)self;
struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *)aux;
bus_space_tag_t iot = sa->sa_iot;
static bus_space_handle_t spi_ioh = 0;
/* we map all registers for SPI0 and SPI1 at once, then
use subregions */
if (spi_ioh == 0) {
if (bus_space_map(iot, S3C2410_SPI0_BASE,
2 * S3C24X0_SPI_SIZE,
0, &spi_ioh)) {
aprint_error(": can't map registers\n");
return;
}
}
aprint_normal("\n");
sc->index = sa->sa_index;
sc->iot = iot;
bus_space_subregion(iot, spi_ioh, sc->index == 0 ? 0 : S3C24X0_SPI_SIZE,
S3C24X0_SPI_SIZE, &sc->ioh);
/*
* Attach child devices
*/
config_search(ssspi_search, self, NULL);
}
void
hpcioman_attach(struct device *parent, struct device *self, void *aux)
{
printf("\n");
config_search(hpcioman_search, self, aux);
}
FILE *
configure ()
{
FILE *rc;
char *home, *temp;
/*
* Open *conf_file, ./.spcrc, ~/.spcrc, /etc/spcrc
*/
if (opt_config) {
if (!strncmp (opt_config, "~/", 2)) {
if (!(home = getenv ("HOME")))
err_quit ("can't find home directory");
temp = malloc (strlen (home)+strlen (opt_config)+1);
strcpy (temp, home);
strcat (temp, opt_config+1);
} else
temp = opt_config;
if (!(rc = config_check (temp)))
err_quit ("can't open config file %s", temp);
free (temp);
return (rc);
}
/*
* look for spcrc-type in the standard locations
*/
if (opt_type) {
opt_config = malloc (strlen (opt_type)+7);
sprintf (opt_config, "spcrc-%s", opt_type);
return (config_search (opt_config));
}
obtain_suffix ();
/*
* look for spcrc-suffix in the standard locations
*/
if (typ_suffix) {
opt_config = malloc (strlen (typ_suffix)+7);
sprintf (opt_config, "spcrc-%s", typ_suffix);
return (config_search (opt_config));
}
err_quit ("can't find a config file");
}
void
shb_attach(struct device *parent, struct device *self, void *aux)
{
printf("\n");
config_search(shb_search, self, NULL);
}
static char *get_control_smtproutes()
{
char *filename=config_search("esmtproutes");
char *buf=readfile(filename, 0);
free(filename);
if (!buf) return (0);
removecomments(buf);
return (buf);
}
const char *config_msgidhost()
{
if (!msgidhost)
{
char *f=config_search("msgidhost");
if ((msgidhost=config_read1l(f)) == 0)
msgidhost=config_me();
free(f);
}
return (msgidhost);
}
void
sbus_attach(struct device *parent, struct device *self, void *aux)
{
int type = BOOTINFO_REF(BOOTINFO_PCMCIA_TYPE);
printf(": controller type %d\n", type);
/* Initialize SBUS controller */
sbus_init(type);
config_search(sbus_search, self, 0);
}
const char *config_me()
{
if (!me)
{
char *f=config_search("me");
if ((me=config_read1l(f)) == 0)
me=config_gethostname();
free(f);
}
return (me);
}
const char *config_esmtphelo()
{
if (!helohost)
{
char *f=config_search("esmtphelo");
if ((helohost=config_read1l(f)) == 0)
helohost=config_me();
free(f);
}
return (helohost);
}
void
obio_attach(struct device *parent, struct device *self, void *aux)
{
struct obio_softc *sc = (struct obio_softc *)self;
struct obiobus_attach_args *oba = aux;
printf("\n");
sc->sc_iot = oba->oba_iot;
sc->sc_memt = oba->oba_memt;
config_search(obio_search, self, NULL);
}
size_t config_dsnlimit()
{
char *f=config_search("dsnlimit");
char *p=config_read1l(f);
size_t l=32768;
if (p)
{
l=atol(p);
free(p);
}
return (l);
}
char *config_dsnfrom()
{
char *f=config_search("dsnfrom");
char *p=config_read1l(f);
static const char defaultdsnfrom[]="\"Courier mail server at %s\" <@>";
free(f);
if (!p)
{
const char *me=config_me();
p=courier_malloc(sizeof(defaultdsnfrom)+strlen(me));
sprintf(p, defaultdsnfrom, me);
}
return (p);
}
void
obio_attach(struct device *parent, struct device *self, void *aux)
{
struct device *sc = self;
obio_found = 1;
printf("\n");
/*
* Attach all the on-board devices as described in the kernel
* configuration file.
*/
config_search(obio_search, self, sc);
}
static void
iic_attach(struct device *parent, struct device *self, void *aux)
{
struct iic_softc *sc = (void *) self;
struct i2cbus_attach_args *iba = aux;
aprint_naive(": I2C bus\n");
aprint_normal(": I2C bus\n");
sc->sc_tag = iba->iba_tag;
/*
* Attach all i2c deviecs described in the kernel
* configuration file.
*/
config_search(iic_search, self, NULL);
}
unsigned long config_sizelimit()
{
char *sizelimitfilename;
if (sizelimit_ptr == 0)
{
sizelimit_ptr=getenv("SIZELIMIT");
if (sizelimit_ptr == 0)
{
sizelimitfilename=config_search("sizelimit");
sizelimit_ptr=config_read1l(sizelimitfilename);
free(sizelimitfilename);
if (sizelimit_ptr == 0)
sizelimit_ptr="10485760";
}
}
return (atol(sizelimit_ptr));
}
void
ixpsip_attach(struct device *parent, struct device *self, void *aux)
{
struct ixpsip_softc *sc = (void *) self;
sc->sc_iot = &ixp425_bs_tag;
ixpsip_softc = sc;
printf("\n");
if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
0, &sc->sc_ioh)) {
printf("%s: Can't map expansion bus control registers!\n",
sc->sc_dev.dv_xname);
return;
}
/*
* Attach each devices
*/
config_search(ixpsip_search, self, NULL);
}
void
pvbus_attach(struct device *parent, struct device *self, void *aux)
{
struct pvbus_softc *sc = (struct pvbus_softc *)self;
int i, cnt;
sc->pvbus_hv = pvbus_hv;
pvbus_softc = sc;
printf(":");
for (i = 0, cnt = 0; i < PVBUS_MAX; i++) {
if (pvbus_hv[i].hv_base == 0)
continue;
if (cnt++)
printf(",");
printf(" %s", pvbus_types[i].name);
if (pvbus_types[i].print != NULL)
(pvbus_types[i].print)(&pvbus_hv[i]);
}
printf("\n");
config_search(pvbus_search, self, sc);
}
void
iic_attach(struct device *parent, struct device *self, void *aux)
{
struct iic_softc *sc = (void *) self;
struct i2cbus_attach_args *iba = aux;
sc->sc_tag = iba->iba_tag;
printf("\n");
/*
* Attach all i2c devices described in the kernel
* configuration file.
*/
config_search(iic_search, self, NULL);
/*
* Scan for known device signatures.
*/
if (iba->iba_bus_scan)
(iba->iba_bus_scan)(self, aux, iba->iba_bus_scan_arg);
else
iic_scan(self, aux);
}
void
mainbus_attach(struct device *parent, struct device *self, void *args)
{
extern void cpu_setup_secondary_processors(void);
extern char cpu_model[];
printf(": %s, cpuid 0x%04x", cpu_model, cpuid);
printf("\n");
/*
* Display cpu/mmu details for the main processor.
*/
cpu_configuration_print(1);
#ifdef MULTIPROCESSOR
/*
* Let secondary processors initialize further and print
* their configuration information now.
*/
cpu_setup_secondary_processors();
#endif
(void)config_search(mainbus_scan, self, args);
}
static char *fetch_smtproutes(const char *domain)
{
char *buf=get_control_smtproutes();
const char *p=buf;
if (!buf)
{
struct dbobj d;
char *p, *q;
size_t l;
p=config_search("esmtproutes.dat");
dbobj_init(&d);
if (dbobj_open(&d, p, "R"))
{
free(p);
return (0);
}
free(p);
p=strcpy(courier_malloc(strlen(domain)+1), domain);
for (q=p; *q; q++)
*q=tolower(*q);
q=dbobj_fetch(&d, p, strlen(p), &l, "D");
free(p);
dbobj_close(&d);
if (!q) return (0);
p=courier_malloc(l+1);
memcpy(p, q, l);
p[l]=0;
free(q);
return (p);
}
while (*p)
{
unsigned i;
for (i=0; p[i] && p[i] != '\n' && p[i] != '\r' && p[i] != ':';
++i)
;
if (p[i] == ':' && (i == 0 ||
config_domaincmp(domain, p, i) == 0))
{
char *q;
p += i;
++p;
for (i=0; p[i] && p[i] != '\n' && p[i] != '\r'; i++)
;
while (i && isspace((int)(unsigned char)p[i-1]))
--i;
while (i && isspace((int)(unsigned char)*p))
{
++p;
--i;
}
if (i == 0)
{
free(buf);
return (0);
}
q=courier_malloc(i+1);
memcpy(q, p, i);
q[i]=0;
free(buf);
return (q);
}
while (p[i])
{
if (p[i] == '\n' || p[i] == '\r')
{
++i;
break;
}
++i;
}
p += i;
}
free(buf);
return (0);
}
void
vmeattach(struct device *parent, struct device *self, void *aux)
{
struct vme_softc *sc = (struct vme_softc *)self;
const struct vme_range *r;
const char *fmt;
u_int32_t ucsr;
int i;
/*
* Set up interrupt handlers.
*/
for (i = 0; i < NVMEINTR; i++)
SLIST_INIT(&vmeintr_handlers[i]);
/*
* Initialize extents
*/
sc->sc_ext_a16 = extent_create("vme a16", 0, 1 << (16 - PAGE_SHIFT),
M_DEVBUF, NULL, 0, EX_NOWAIT);
if (sc->sc_ext_a16 == NULL)
goto out1;
sc->sc_ext_a24 = extent_create("vme a24", 0, 1 << (24 - PAGE_SHIFT),
M_DEVBUF, NULL, 0, EX_NOWAIT);
if (sc->sc_ext_a24 == NULL)
goto out2;
sc->sc_ext_a32 = extent_create("vme a32", 0, 1 << (32 - PAGE_SHIFT),
M_DEVBUF, NULL, 0, EX_NOWAIT);
if (sc->sc_ext_a32 == NULL)
goto out3;
/*
* Force a reasonable timeout for VME data transfers.
* We can not disable this, this would cause autoconf to hang
* on the first missing device we'll probe.
*/
ucsr = *(volatile u_int32_t*)AV_UCSR;
ucsr = (ucsr & ~VTOSELBITS) | VTO128US;
*(volatile u_int32_t *)AV_UCSR = ucsr;
/*
* Clear EXTAD to allow VME A24 devices to access the first 16MB
* of memory.
*/
*(volatile u_int32_t *)AV_EXTAD = 0x00000000;
/*
* Use supervisor data address modifiers for VME accesses.
*/
*(volatile u_int32_t *)AV_EXTAM = 0x0d;
sc->sc_ranges = platform->get_vme_ranges();
printf("\n");
/*
* Display VME ranges.
*/
for (r = sc->sc_ranges; r->vr_width != 0; r++) {
switch (r->vr_width) {
default:
case VME_A32:
fmt = "%s: A32 %08x-%08x\n";
break;
case VME_A24:
fmt = "%s: A24 %06x-%06x\n";
break;
case VME_A16:
fmt = "%s: A16 %04x-%04x\n";
break;
}
printf(fmt, self->dv_xname, r->vr_start, r->vr_end);
}
/* scan for child devices */
config_search(vmescan, self, aux);
return;
out3:
extent_destroy(sc->sc_ext_a24);
out2:
extent_destroy(sc->sc_ext_a16);
out1:
printf(": can't allocate memory\n");
}
void
gio_attach(struct device *parent, struct device *self, void *aux)
{
struct gio_softc *sc = (struct gio_softc *)self;
struct imc_attach_args *iaa = (struct imc_attach_args *)aux;
struct gio_attach_args ga;
uint32_t gfx[GIO_MAX_FB], id;
uint i, j, ngfx;
int sys_type;
printf("\n");
sc->sc_iot = iaa->iaa_st;
sc->sc_dmat = iaa->iaa_dmat;
switch (sys_config.system_type) {
case SGI_IP20:
sys_type = SGI_IP20;
break;
default:
case SGI_IP22:
case SGI_IP26:
case SGI_IP28:
sys_type = SGI_IP22;
break;
}
ngfx = 0;
memset(gfx, 0, sizeof(gfx));
/*
* Try and attach graphics devices first.
* Unfortunately, they - not being GIO devices after all - do not
* contain a Product Identification Word, nor have a slot number.
*
* Record addresses to which graphics devices attach so that
* we do not confuse them with expansion slots, should the
* addresses coincide.
*
* If only the ARCBios component tree would be so kind as to give
* us the address of the frame buffer components...
*/
if (sys_type != SGI_IP22 ||
sys_config.system_subtype != IP22_CHALLS) {
for (i = 0; gfx_bases[i].base != 0; i++) {
/* skip slots that don't apply to us */
if (gfx_bases[i].mach_type != sys_type)
continue;
if (gfx_bases[i].mach_subtype != -1 &&
gfx_bases[i].mach_subtype !=
sys_config.system_subtype)
continue;
ga.ga_addr = gfx_bases[i].base;
ga.ga_ioh = PHYS_TO_XKPHYS(ga.ga_addr, CCA_NC);
/* no need to probe a glass console again */
if (ga.ga_addr == giofb_consaddr && giofb_consid != 0)
id = giofb_consid;
else {
id = gio_id(ga.ga_ioh, ga.ga_addr, 1);
if (!gio_is_framebuffer_id(id))
continue;
}
ga.ga_iot = sc->sc_iot;
ga.ga_dmat = sc->sc_dmat;
ga.ga_slot = -1;
ga.ga_product = id;
/*
* Note that this relies upon ARCBios listing frame
* buffers in ascending address order, which seems
* to be the case so far on multihead Indigo2 systems.
*/
if (ngfx < GIO_MAX_FB)
ga.ga_descr = giofb_names[ngfx];
else
ga.ga_descr = NULL; /* shouldn't happen */
if (config_found_sm(self, &ga, gio_print_fb,
gio_submatch))
gfx[ngfx] = gfx_bases[i].base;
ngfx++;
}
}
/*
* Now attach any GIO expansion cards.
*
* Be sure to skip any addresses to which a graphics device has
* already been attached.
*/
for (i = 0; slot_bases[i].base != 0; i++) {
int skip = 0;
/* skip slots that don't apply to us */
if (slot_bases[i].mach_type != sys_type)
continue;
if (slot_bases[i].mach_subtype != -1 &&
slot_bases[i].mach_subtype != sys_config.system_subtype)
continue;
for (j = 0; j < ngfx; j++) {
if (slot_bases[i].base == gfx[j]) {
skip = 1;
break;
}
}
if (skip)
continue;
ga.ga_addr = slot_bases[i].base;
ga.ga_iot = sc->sc_iot;
ga.ga_ioh = PHYS_TO_XKPHYS(ga.ga_addr, CCA_NC);
id = gio_id(ga.ga_ioh, ga.ga_addr, 0);
if (id == 0)
continue;
ga.ga_dmat = sc->sc_dmat;
ga.ga_slot = slot_bases[i].slot;
ga.ga_product = id;
ga.ga_descr = NULL;
config_found_sm(self, &ga, gio_print, gio_submatch);
}
config_search(gio_search, self, aux);
}
void
glxpcib_attach(struct device *parent, struct device *self, void *aux)
{
struct glxpcib_softc *sc = (struct glxpcib_softc *)self;
struct timecounter *tc = &sc->sc_timecounter;
#ifndef SMALL_KERNEL
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
u_int64_t wa;
#if NGPIO > 0
u_int64_t ga;
struct gpiobus_attach_args gba;
int i, gpio = 0;
#endif
u_int64_t sa;
struct i2cbus_attach_args iba;
int i2c = 0;
bus_space_handle_t tmpioh;
#endif
tc->tc_get_timecount = glxpcib_get_timecount;
tc->tc_counter_mask = 0xffffffff;
tc->tc_frequency = 3579545;
tc->tc_name = "CS5536";
tc->tc_quality = 1000;
tc->tc_priv = sc;
tc_init(tc);
printf(": rev %d, 32-bit %lluHz timer",
(int)rdmsr(AMD5536_REV) & AMD5536_REV_MASK,
tc->tc_frequency);
#ifndef SMALL_KERNEL
/* Attach the watchdog timer */
sc->sc_iot = pa->pa_iot;
wa = rdmsr(MSR_LBAR_MFGPT);
if (wa & MSR_LBAR_ENABLE &&
!bus_space_map(sc->sc_iot, wa & MSR_MFGPT_ADDR_MASK,
MSR_MFGPT_SIZE, 0, &sc->sc_ioh)) {
/* count in seconds (as upper level desires) */
bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMD5536_MFGPT0_SETUP,
AMD5536_MFGPT_CNT_EN | AMD5536_MFGPT_CMP2EV |
AMD5536_MFGPT_CMP2 | AMD5536_MFGPT_DIV_MASK |
AMD5536_MFGPT_STOP_EN);
wdog_register(glxpcib_wdogctl_cb, sc);
sc->sc_wdog = 1;
printf(", watchdog");
}
#if NGPIO > 0
/* map GPIO I/O space */
sc->sc_gpio_iot = pa->pa_iot;
ga = rdmsr(MSR_LBAR_GPIO);
if (ga & MSR_LBAR_ENABLE &&
!bus_space_map(sc->sc_gpio_iot, ga & MSR_GPIO_ADDR_MASK,
MSR_GPIO_SIZE, 0, &sc->sc_gpio_ioh)) {
printf(", gpio");
/* initialize pin array */
for (i = 0; i < AMD5536_GPIO_NPINS; i++) {
sc->sc_gpio_pins[i].pin_num = i;
sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT |
GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN |
GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN |
GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
/* read initial state */
sc->sc_gpio_pins[i].pin_state =
glxpcib_gpio_pin_read(sc, i);
}
/* create controller tag */
sc->sc_gpio_gc.gp_cookie = sc;
sc->sc_gpio_gc.gp_pin_read = glxpcib_gpio_pin_read;
sc->sc_gpio_gc.gp_pin_write = glxpcib_gpio_pin_write;
sc->sc_gpio_gc.gp_pin_ctl = glxpcib_gpio_pin_ctl;
gba.gba_name = "gpio";
gba.gba_gc = &sc->sc_gpio_gc;
gba.gba_pins = sc->sc_gpio_pins;
gba.gba_npins = AMD5536_GPIO_NPINS;
gpio = 1;
}
#endif /* NGPIO */
/* Map SMB I/O space */
sc->sc_smb_iot = pa->pa_iot;
sa = rdmsr(MSR_LBAR_SMB);
if (sa & MSR_LBAR_ENABLE &&
!bus_space_map(sc->sc_smb_iot, sa & MSR_SMB_ADDR_MASK,
MSR_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
printf(", i2c");
/* Enable controller */
bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
AMD5536_SMB_CTL2, AMD5536_SMB_CTL2_EN |
AMD5536_SMB_CTL2_FREQ);
/* Disable interrupts */
bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
AMD5536_SMB_CTL1, 0);
/* Disable slave address */
bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
AMD5536_SMB_ADDR, 0);
/* Stall the bus after start */
bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh,
AMD5536_SMB_CTL1, AMD5536_SMB_CTL1_STASTRE);
/* Attach I2C framework */
sc->sc_smb_ic.ic_cookie = sc;
sc->sc_smb_ic.ic_acquire_bus = glxpcib_smb_acquire_bus;
sc->sc_smb_ic.ic_release_bus = glxpcib_smb_release_bus;
sc->sc_smb_ic.ic_send_start = glxpcib_smb_send_start;
sc->sc_smb_ic.ic_send_stop = glxpcib_smb_send_stop;
sc->sc_smb_ic.ic_initiate_xfer = glxpcib_smb_initiate_xfer;
sc->sc_smb_ic.ic_read_byte = glxpcib_smb_read_byte;
sc->sc_smb_ic.ic_write_byte = glxpcib_smb_write_byte;
rw_init(&sc->sc_smb_lck, "iiclk");
bzero(&iba, sizeof(iba));
iba.iba_name = "iic";
iba.iba_tag = &sc->sc_smb_ic;
i2c = 1;
}
/* Map PMS I/O space and enable the ``Power Immediate'' feature */
sa = rdmsr(MSR_LBAR_PMS);
if (sa & MSR_LBAR_ENABLE &&
!bus_space_map(pa->pa_iot, sa & MSR_PMS_ADDR_MASK,
MSR_PMS_SIZE, 0, &tmpioh)) {
bus_space_write_4(pa->pa_iot, tmpioh, AMD5536_PMS_SSC,
AMD5536_PMS_SSC_SET_PI);
bus_space_barrier(pa->pa_iot, tmpioh, AMD5536_PMS_SSC, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
bus_space_unmap(pa->pa_iot, tmpioh, MSR_PMS_SIZE);
}
#endif /* SMALL_KERNEL */
pcibattach(parent, self, aux);
#ifndef SMALL_KERNEL
#if NGPIO > 0
if (gpio)
config_found(&sc->sc_dev, &gba, gpiobus_print);
#endif
if (i2c)
config_found(&sc->sc_dev, &iba, iicbus_print);
config_search(glxpcib_search, self, pa);
#endif
}
void
s3c2800_attach(struct device *parent, struct device *self, void *aux)
{
struct s3c2800_softc *sc = (struct s3c2800_softc *) self;
bus_space_tag_t iot;
const char *which_registers; /* for panic message */
#define FAIL(which) do { \
which_registers=(which); goto abort; }while(/*CONSTCOND*/0)
s3c2xx0_softc = &(sc->sc_sx);
sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
if (bus_space_map(iot,
S3C2800_INTCTL_BASE, S3C2800_INTCTL_SIZE,
BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh))
FAIL("intc");
/* tell register addresses to interrupt handler */
s3c2800_intr_init(sc);
/* Map the GPIO registers */
if (bus_space_map(iot, S3C2800_GPIO_BASE, S3C2800_GPIO_SIZE,
0, &sc->sc_sx.sc_gpio_ioh))
FAIL("GPIO");
#if 0
/* Map the DMA controller registers */
if (bus_space_map(iot, S3C2800_DMAC_BASE, S3C2800_DMAC_SIZE,
0, &sc->sc_sx.sc_dmach))
FAIL("DMAC");
#endif
/* Memory controller */
if (bus_space_map(iot, S3C2800_MEMCTL_BASE,
S3C2800_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
FAIL("MEMC");
/* Clock manager */
if (bus_space_map(iot, S3C2800_CLKMAN_BASE,
S3C2800_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
FAIL("CLK");
#if 0
/* Real time clock */
if (bus_space_map(iot, S3C2800_RTC_BASE,
S3C2800_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
FAIL("RTC");
#endif
if (bus_space_map(iot, S3C2800_TIMER0_BASE,
S3C2800_TIMER_SIZE, 0, &sc->sc_tmr0_ioh))
FAIL("TIMER0");
if (bus_space_map(iot, S3C2800_TIMER1_BASE,
S3C2800_TIMER_SIZE, 0, &sc->sc_tmr1_ioh))
FAIL("TIMER1");
/* calculate current clock frequency */
s3c2800_clock_freq(&sc->sc_sx);
aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
sc->sc_sx.sc_pclk / 1000000);
aprint_naive("\n");
/*
* Attach devices.
*/
config_search(s3c2800_search, self, NULL);
return;
abort:
panic("%s: unable to map %s registers",
self->dv_xname, which_registers);
#undef FAIL
}
