void main(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); timestamp_add_now(TS_END_ROMSTAGE); run_ramstage(); }
void main(void) { #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif #if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) void *entry = vboot2_load_ramstage(); if (entry != NULL) stage_exit(entry); #endif run_ramstage(); }
void board_init_f(ulong dummy) { struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ /* Enable early UART on the RK3288 */ struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ #include <asm/arch/grf_rk3288.h> /* Enable early UART on the RK3288 */ #define GRF_BASE 0xff770000 struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } #if !defined(CONFIG_SPL_OF_PLATDATA) if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { ret = phycore_init(); if (ret) { debug("Failed to set up phycore power settings: %d\n", ret); return; } } #endif #if !defined(CONFIG_SUPPORT_TPL) debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } #endif #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }