/* Handle a request to unlock the cache line containing the given address. */
void
frv_cache_request_unlock (FRV_CACHE *cache, SI address, int slot)
{
FRV_CACHE_REQUEST *req;
/* slot is a UNIT_*. Convert it to a cache pipeline index. */
int pipe = convert_slot_to_index (slot);
FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
/* Add the load request to the indexed pipeline. */
req = new_cache_request ();
req->kind = req_unlock;
req->reqno = NO_REQNO;
req->priority = next_priority (cache, pipeline);
req->address = address;
pipeline_add_request (pipeline, req);
}
/* Handle a request to invalidate the cache line containing the given address.
Flush the data if requested. */
void
frv_cache_request_invalidate (FRV_CACHE *cache, unsigned reqno, SI address,
int slot, int all, int flush)
{
FRV_CACHE_REQUEST *req;
/* slot is a UNIT_*. Convert it to a cache pipeline index. */
int pipe = convert_slot_to_index (slot);
FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
/* Add the load request to the indexed pipeline. */
req = new_cache_request ();
req->kind = req_invalidate;
req->reqno = reqno;
req->priority = next_priority (cache, pipeline);
req->address = address;
req->u.invalidate.all = all;
req->u.invalidate.flush = flush;
pipeline_add_request (pipeline, req);
}
void
frv_cache_request_store (FRV_CACHE *cache, SI address,
int slot, char *data, unsigned length)
{
FRV_CACHE_REQUEST *req;
/* slot is a UNIT_*. Convert it to a cache pipeline index. */
int pipe = convert_slot_to_index (slot);
FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
/* Add the load request to the indexed pipeline. */
req = new_store_request (length);
req->kind = req_store;
req->reqno = NO_REQNO;
req->priority = next_priority (cache, pipeline);
req->address = address;
req->u.store.length = length;
memcpy (req->u.store.data, data, length);
pipeline_add_request (pipeline, req);
invalidate_return_buffer (cache, address);
}
/* Handle a request to preload the cache line containing the given address. */
void
frv_cache_request_preload (FRV_CACHE *cache, SI address,
int slot, int length, int lock)
{
FRV_CACHE_REQUEST *req;
/* slot is a UNIT_*. Convert it to a cache pipeline index. */
int pipe = convert_slot_to_index (slot);
FRV_CACHE_PIPELINE *pipeline = & cache->pipeline[pipe];
/* Add the load request to the indexed pipeline. */
req = new_cache_request ();
req->kind = req_preload;
req->reqno = NO_REQNO;
req->priority = next_priority (cache, pipeline);
req->address = address;
req->u.preload.length = length;
req->u.preload.lock = lock;
pipeline_add_request (pipeline, req);
invalidate_return_buffer (cache, address);
}