int checkboard(void)
{
#ifndef CONFIG_CPCI405_VER2
int index;
int len;
#endif
char str[64];
int i = getenv_f("serial#", str, sizeof(str));
unsigned short ver;
puts("Board: ");
if (i == -1)
puts("### No HW ID - assuming CPCI405");
else
puts(str);
ver = cpci405_version();
printf(" (Ver %d.x, ", ver);
if (ctermm2()) {
char str[4];
/*
* Read board-id and save in env-variable
*/
sprintf(str, "%d", *(unsigned char *)0xf0000400);
setenv("boardid", str);
printf("CTERM-M2 - Id=%s)", str);
} else {
if (cpci405_host())
puts("PCI Host Version)");
else
puts("PCI Adapter Version)");
}
#ifndef CONFIG_CPCI405_VER2
puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf("%s ", &(fpgadata[index + 1]));
index += len + 3;
}
#endif
putc('\n');
return 0;
}
int board_early_init_f (void)
{
#ifndef CONFIG_CPCI405_VER2
int index, len, i;
int status;
#endif
#ifdef FPGA_DEBUG
DECLARE_GLOBAL_DATA_PTR;
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
console_init_f();
#endif
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
out32(GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
*/
#ifndef CONFIG_CPCI405_VER2
if (cpci405_version() == 1) {
status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
if (status != 0) {
/* booting FPGA failed */
#ifndef FPGA_DEBUG
DECLARE_GLOBAL_DATA_PTR;
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
console_init_f();
#endif
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = fpgadata[index];
printf("FPGA: %s\n", &(fpgadata[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc ('\n');
do_reset(NULL, 0, 0, NULL);
}
}
#endif /* !CONFIG_CPCI405_VER2 */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd = gd->bd;
char * tmp; /* Temporary char pointer */
unsigned long cntrl0Reg;
#ifdef CONFIG_CPCI405_VER2
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
/*
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc ('\n');
do_reset(NULL, 0, 0, NULL);
}
/* restore gpio/cs settings */
mtdcr(cntrl0, cntrl0Reg);
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
}
putc ('\n');
free(dst);
/*
* Reset FPGA via FPGA_DATA pin
*/
SET_FPGA(FPGA_PRG | FPGA_CLK);
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
/*
* Enable outputs in fpga on version 3 board
*/
*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
/*
* Set outputs to 0
*/
*leds = 0x00;
/*
* Reset external DUART
*/
*fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
udelay(100);
*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
}
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Version 1.x detected!\n");
puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
}
#else /* CONFIG_CPCI405_VER2 */
/*
* Generate last byte of ip-addr from code-plug @ 0xf0000400
*/
if (ctermm2()) {
char str[32];
unsigned char ipbyte = *(unsigned char *)0xf0000400;
/*
* Only overwrite ip-addr with allowed values
*/
if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
sprintf(str, "%ld.%ld.%ld.%ld",
(bd->bi_ip_addr & 0xff000000) >> 24,
(bd->bi_ip_addr & 0x00ff0000) >> 16,
(bd->bi_ip_addr & 0x0000ff00) >> 8,
(bd->bi_ip_addr & 0x000000ff));
setenv("ipaddr", str);
}
}
int misc_init_r (void)
{
unsigned long CPC0_CR0Reg;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_CPCI405_VER2)
{
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
/*
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
(uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after "
"asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after "
"deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after "
"programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index + 1]));
index += len + 3;
}
putc('\n');
/* delayed reboot */
for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r", i);
for (index = 0; index < 1000; index++)
udelay(1000);
}
putc('\n');
do_reset(NULL, 0, 0, NULL);
}
/* restore gpio/cs settings */
mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = dst[index];
printf("%s ", &(dst[index + 1]));
index += len + 3;
}
putc('\n');
free(dst);
/*
* Reset FPGA via FPGA_DATA pin
*/
SET_FPGA(FPGA_PRG | FPGA_CLK);
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
#if defined(CONFIG_CPCI405_6U)
#error HIER GETH ES WEITER MIT IO ACCESSORS
if (cpci405_version() == 3) {
/*
* Enable outputs in fpga on version 3 board
*/
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
/*
* Set outputs to 0
*/
out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
/*
* Reset external DUART
*/
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
CONFIG_SYS_FPGA_MODE_DUART_RESET);
udelay(100);
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
~CONFIG_SYS_FPGA_MODE_DUART_RESET);
}
#endif
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Version 1.x detected!\n");
puts("*** Please use correct U-Boot version "
"(CPCI405 instead of CPCI4052)!\n\n");
}
}
#else /* CONFIG_CPCI405_VER2 */
if (cpci405_version() >= 2) {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Board Version 2.x detected!\n");
puts("*** Please use correct U-Boot version "
"(CPCI4052 instead of CPCI405)!\n\n");
}
#endif /* CONFIG_CPCI405_VER2 */
/*
* Select cts (and not dsr) on uart1
*/
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
return 0;
}
