void __init cpm_reset(void)
{
#ifndef CONFIG_FPGA_TEST
unsigned long clkgr0 = cpm_inl(CPM_CLKGR0);
unsigned long clkgr1 = cpm_inl(CPM_CLKGR1);
unsigned long lcr = cpm_inl(CPM_LCR);
#if 1
cpm_outl(clkgr1 & ~(1<<2|1<<4),CPM_CLKGR1);
mdelay(1);
cpm_outl(clkgr0 & ~(1<<26|1<<27|1<<28),CPM_CLKGR0);
mdelay(1);
cpm_outl(0x27f87ffe,CPM_CLKGR0);
mdelay(1);
cpm_outl(0xfffffdff,CPM_CLKGR1);
mdelay(1);
#endif
cpm_outl(lcr | CPM_LCR_PD_MASK | 0x8f<<8,CPM_LCR);
while((cpm_inl(CPM_LCR) & (0x7<<24)) != (0x7<<24));
cpm_outl(0,CPM_PSWC0ST);
cpm_outl(16,CPM_PSWC1ST);
cpm_outl(24,CPM_PSWC2ST);
cpm_outl(8,CPM_PSWC3ST);
#endif
}
void __init init_gate_clk(struct clk *clk)
{
int id = 0;
static unsigned long clkgr[2]={0};
static int clkgr_init = 0;
int bit = CLK_GATE_BIT(clk->flags);
if(clkgr_init == 0){
clkgr[0] = cpm_inl(CPM_CLKGR);
clkgr_init = 1;
}
if (clk->flags & CLK_FLG_PARENT) {
id = CLK_PARENT(clk->flags);
clk->parent = get_clk_from_id(id);
}else
clk->parent = get_clk_from_id(CLK_ID_EXT1);
clk->rate = clk_get_rate(clk->parent);
if(clkgr[bit / 32] & (1 << (bit % 32))) {
clk->flags &= ~(CLK_FLG_ENABLE);
//cpm_gate_enable(clk,0);
}else {
clk->flags |= CLK_FLG_ENABLE;
//cpm_gate_enable(clk,1);
}
clk->ops = &clk_gate_ops;
}
void pll_init(void)
{
unsigned int cpccr = 0;
debug("pll init...");
#ifdef CONFIG_BURNER
cpccr = (0x95 << 24) | (7 << 20);
cpm_outl(cpccr,CPM_CPCCR);
while(cpm_inl(CPM_CPCSR) & 0x7);
#endif
/* Only apll is init here */
cpm_outl(get_pllreg_value(APLL) | (0x1 << 8) | 0x20,CPM_CPAPCR);
while(!(cpm_inl(CPM_CPAPCR) & (0x1<<10)));
debug("CPM_CPAPCR %x\n", cpm_inl(CPM_CPAPCR));
cpccr = (cpm_inl(CPM_CPCCR) & (0xff << 24))
| (CPCCR_CFG & ~(0xff << 24))
| (7 << 20);
cpm_outl(cpccr,CPM_CPCCR);
while(cpm_inl(CPM_CPCSR) & 0x7);
cpccr = (CPCCR_CFG & (0xff << 24)) | (cpm_inl(CPM_CPCCR) & ~(0xff << 24));
cpm_outl(cpccr,CPM_CPCCR);
while(cpm_inl(CPM_CPCSR) & 0x7);
debug("ok\n");
}
static int vpu_reset(struct jz_vpu *vpu)
{
int timeout = 0xffffff;
unsigned int srbc = cpm_inl(CPM_SRBC);
cpm_set_bit(30, CPM_SRBC);
while (!(cpm_inl(CPM_SRBC) & (1 << 29)) && --timeout);
if (timeout == 0) {
dev_warn(vpu->dev, "[%d:%d] wait stop ack timeout\n",
current->tgid, current->pid);
cpm_outl(srbc, CPM_SRBC);
return -1;
} else {
cpm_outl(srbc | (1 << 31), CPM_SRBC);
cpm_outl(srbc, CPM_SRBC);
}
return 0;
}
int dump_out_clk(char* str,DUMP_CALLBACK dump_callback)
{
int i;
int len = 0;
// len += dump_callback(str + len,"ID NAME FRE stat count parent\n");
for(i = 0; i < ARRAY_SIZE(clk_srcs); i++) {
if (clk_srcs[i].name == NULL) {
//len += dump_callback(str + len,"--------------------------------------------------------\n");
} else {
unsigned int mhz = clk_srcs[i].rate / 10000;
len += dump_callback(str + len,"%2d %-10s %4d.%02dMHz %3sable %d %s\n",i,clk_srcs[i].name
, mhz/100, mhz%100
, clk_srcs[i].flags & CLK_FLG_ENABLE? "en": "dis"
, clk_srcs[i].count
, clk_srcs[i].parent? clk_srcs[i].parent->name: "root");
}
}
len += dump_callback(str + len,"CLKGR\t: %08x\n",cpm_inl(CPM_CLKGR));
len += dump_callback(str + len,"LCR1\t: %08x\n",cpm_inl(CPM_LCR));
return len;
}
void pll_init(void)
{
unsigned int cpccr;
unsigned int cppcr = cpm_inl(CPM_CPPCR);
cppcr &= ~(0xfff << 8); //BWADJ value
cppcr |= 16 << 8 | 0xff | (0x1 << 30); //stable delay to MAX, Fastlock mode enable
cpm_outl(cppcr,CPM_CPPCR);
struct global_info *ginfo = CONFIG_SPL_GINFO_BASE;
unsigned int mpll_value;
unsigned int tmp = ginfo->cpufreq / ginfo->ddrfreq;
if(tmp < 1)
tmp = 1;
mpll_value = nfro(ginfo->extal,ginfo->ddrfreq * tmp);
cpm_outl(mpll_value | 0x1,CPM_CPMPCR);
while(!(cpm_inl(CPM_CPMPCR) & (0x1<<4)));
if(ginfo->cpufreq > 1000000000) {
cpccr = CPCCR_CFG(2,2,2,2,12,6,tmp,2,1) | (7 << 20);
}else if(ginfo->cpufreq > 800000000){
cpccr = CPCCR_CFG(2,2,2,2,8,4,tmp,2,1) | (7 << 20);
}else if(ginfo->cpufreq > 600000000){
cpccr = CPCCR_CFG(2,2,2,2,6,3,tmp,2,1) | (7 << 20);
}else {
cpccr = CPCCR_CFG(2,2,2,2,4,2,tmp,2,1) | (7 << 20);
}
printf("cpuspeed:%d\n",ginfo->cpufreq);
printf("ddrspeed:%d\n",ginfo->ddrfreq);
printf("tmp:%d\n",tmp);
printf("cpccr:%x\n",cpccr);
cpm_outl(cpccr,CPM_CPCCR);
while(cpm_inl(CPM_CPCSR) & 0x7);
// print_clock() ;
}
void __init cpm_reset(void)
{
#ifndef CONFIG_FPGA_TEST
unsigned long clkgr = cpm_inl(CPM_CLKGR);
clkgr &= ~(1 << 28 /* DES */
| 1 << 26 /* TVE */
| 1 << 13 /* SADC */
);
cpm_outl(clkgr, CPM_CLKGR);
/* TODO set default clkgr here */
#endif
}
void __init cpm_reset(void)
{
#ifndef CONFIG_FPGA_TEST
unsigned long clkgr = cpm_inl(CPM_CLKGR);
#if 1
cpm_outl(clkgr & ~(1<<19|1<<23|1<<24|1<<25),CPM_CLKGR);
mdelay(1);
//cpm_outl(0x27f87ffe,CPM_CLKGR);
#ifdef CONFIG_NAND_DRIVER
cpm_outl(0x7de87ffe,CPM_CLKGR);
#else
cpm_outl(0x7df87ffe,CPM_CLKGR);
#endif
mdelay(1);
#endif
cpm_pwc_init();
#endif
}
static int vpu_on(struct jz_vpu *vpu)
{
if (cpm_inl(CPM_OPCR) & OPCR_IDLE)
return -EBUSY;
clk_enable(vpu->clk_gate);
__asm__ __volatile__ (
"mfc0 $2, $16, 7 \n\t"
"ori $2, $2, 0x340 \n\t"
"andi $2, $2, 0x3ff \n\t"
"mtc0 $2, $16, 7 \n\t"
"nop \n\t");
vpu_reset(vpu);
enable_irq(vpu->irq);
wake_lock(&vpu->wake_lock);
dev_dbg(vpu->dev, "[%d:%d] on\n", current->tgid, current->pid);
return 0;
}
void __init cpm_reset(void)
{
unsigned int cpm_clkgr;
cpm_clkgr = cpm_inl(CPM_CLKGR);
cpm_clkgr |= 0x07de3ffe;
/* default open pdma clk gate */
cpm_clkgr &= ~(1 << 20);
/* default open tcu clk gate */
cpm_clkgr &= ~(1 << 18);
#ifdef CONFIG_TIMER_SYS_OST
cpm_clkgr &= ~(1 << 20);
#endif
cpm_outl(cpm_clkgr, CPM_CLKGR);
cpm_outl(0,CPM_PSWC0ST);
cpm_outl(16,CPM_PSWC1ST);
cpm_outl(24,CPM_PSWC2ST);
cpm_outl(8,CPM_PSWC3ST);
}
void __init cpm_reset(void)
{
#ifndef CONFIG_FPGA_TEST
unsigned int cpm_clkgr;
cpm_clkgr = cpm_inl(CPM_CLKGR);
cpm_clkgr |= 0x5ed83fff;
cpm_clkgr &= (~(1 << 21));
/* keep dsi and lcd clock on */
cpm_clkgr &= (~(1 << 24));
cpm_clkgr &= (~(1 << 26));
cpm_outl(cpm_clkgr, CPM_CLKGR);
cpm_outl(0x29ff, CPM_CLKGR1);
cpm_outl(0x08000000, CPM_USBCDR);
/* warn:when switch cpu freq ,the 23(sclka mux) bit should be set */
cpm_set_bit(23,CPM_CPCCR);
mdelay(1);
#endif
}
void jz_wdt_restart(char *command)
{
printk("Restarting after 4 ms\n");
if ((command != NULL) && !strcmp(command, "recovery")) {
while(cpm_inl(CPM_CPPSR) != RECOVERY_SIGNATURE) {
printk("set RECOVERY_SIGNATURE\n");
cpm_outl(0x5a5a,CPM_CPSPPR);
cpm_outl(RECOVERY_SIGNATURE,CPM_CPPSR);
cpm_outl(0x0,CPM_CPSPPR);
udelay(100);
}
} else {
cpm_outl(0x5a5a,CPM_CPSPPR);
cpm_outl(REBOOT_SIGNATURE,CPM_CPPSR);
cpm_outl(0x0,CPM_CPSPPR);
}
wdt_start_count(4);
mdelay(200);
while(1)
printk("check wdt.\n");
}
void jz_otg_phy_init(otg_mode_t mode)
{
unsigned int usbpcr1;
/* select dwc otg */
cpm_set_bit(8, CPM_USBPCR1);
cpm_set_bit(9, CPM_USBPCR1);
cpm_set_bit(28, CPM_USBPCR1);
cpm_set_bit(29, CPM_USBPCR1);
cpm_set_bit(30, CPM_USBPCR1);
/* select utmi data bus width of port0 to 16bit/30M */
cpm_clear_bit(USBPCR1_WORD_IF0, CPM_USBPCR1);
/* select utmi data bus width of port0 to 8bit/60M */
/*cpm_set_bit(USBPCR1_WORD_IF0, CPM_USBPCR1);*/
usbpcr1 = cpm_inl(CPM_USBPCR1);
usbpcr1 &= ~(0x7 << 23);
usbpcr1 |= (5 << 23);
cpm_outl(usbpcr1, CPM_USBPCR1);
/* fil */
cpm_outl(0, CPM_USBVBFIL);
/* rdt */
cpm_outl(0x96, CPM_USBRDT);
/* rdt - filload_en */
cpm_set_bit(USBRDT_VBFIL_LD_EN, CPM_USBRDT);
/* TXRISETUNE & TXVREFTUNE. */
//cpm_outl(0x3f, CPM_USBPCR);
//cpm_outl(0x35, CPM_USBPCR);
/* enable tx pre-emphasis */
//cpm_set_bit(USBPCR_TXPREEMPHTUNE, CPM_USBPCR);
/* OTGTUNE adjust */
//cpm_outl(7 << 14, CPM_USBPCR);
cpm_outl(0x8380385a, CPM_USBPCR);
if (mode == DEVICE_ONLY) {
printk("DWC IN DEVICE ONLY MODE\n");
cpm_clear_bit(USBPCR_USB_MODE, CPM_USBPCR);
cpm_clear_bit(USBPCR_OTG_DISABLE, CPM_USBPCR);
cpm_clear_bit(USBPCR_SIDDQ, CPM_USBPCR);
} else {
unsigned int tmp;
printk("DWC IN OTG MODE\n");
tmp = cpm_inl(CPM_USBPCR);
tmp |= 1 << USBPCR_USB_MODE | 1 << USBPCR_COMMONONN;
tmp &= ~(1 << USBPCR_OTG_DISABLE | 1 << USBPCR_SIDDQ |
0x03 << USBPCR_IDPULLUP_MASK | 1 << USBPCR_VBUSVLDEXT |
1 << USBPCR_VBUSVLDEXTSEL);
cpm_outl(tmp, CPM_USBPCR);
}
/*cpm_set_bit(USBRDT_UTMI_RST, CPM_USBRDT);*/
/*udelay(10);*/
cpm_set_bit(USBPCR_POR, CPM_USBPCR);
cpm_clear_bit(USBRDT_UTMI_RST, CPM_USBRDT);
cpm_set_bit(SRBC_USB_SR, CPM_SRBC);
udelay(5);
cpm_clear_bit(USBPCR_POR, CPM_USBPCR);
udelay(10);
cpm_set_bit(OPCR_SPENDN0, CPM_OPCR);
udelay(550);
cpm_set_bit(USBRDT_UTMI_RST, CPM_USBRDT);
udelay(10);
cpm_clear_bit(SRBC_USB_SR, CPM_SRBC);
}
int cpm_start_ohci(void)
{
int tmp;
static int has_reset = 0;
/* The PLL uses CLKCORE as reference */
tmp = cpm_inl(CPM_USBPCR1);
tmp |= (0x3<<26);
cpm_outl(tmp,CPM_USBPCR1);
/* selects the reference clock frequency 48M */
tmp = cpm_inl(CPM_USBPCR1);
tmp &= ~(0x3<<24);
switch(JZ_EXTAL) {
case 24000000:
tmp |= (1<<24);break;
case 48000000:
tmp |= (2<<24);break;
case 19200000:
tmp |= (3<<24);break;
case 12000000:
default:
tmp |= (0<<24);break;
}
cpm_outl(tmp,CPM_USBPCR1);
/* Configurate UHC IBSOP */
tmp = cpm_inl(CPM_USBPCR1);
tmp &= ~(7 << 14);
tmp |= (1 << 14);
cpm_outl(tmp,CPM_USBPCR1);
/* Configurate UHC XP */
tmp = cpm_inl(CPM_USBPCR1);
tmp &= ~(3 << 12);
cpm_outl(tmp,CPM_USBPCR1);
/* Configurate UHC SP */
tmp = cpm_inl(CPM_USBPCR1);
tmp &= ~(7 << 9);
tmp |= (1 << 9);
cpm_outl(tmp,CPM_USBPCR1);
/* Configurate UHC SM */
tmp = cpm_inl(CPM_USBPCR1);
tmp &= ~(7 << 6);
tmp |= (1 << 6);
cpm_outl(tmp,CPM_USBPCR1);
/* Disable overcurrent */
cpm_clear_bit(4,CPM_USBPCR1);
/* Enable OHCI clock */
cpm_set_bit(5,CPM_USBPCR1);
cpm_set_bit(17,CPM_USBPCR1);
cpm_set_bit(6, CPM_OPCR);
/* OTG PHY reset */
cpm_set_bit(22, CPM_USBPCR);
udelay(30);
cpm_clear_bit(22, CPM_USBPCR);
udelay(300);
/* UHC soft reset */
if(!has_reset) {
cpm_set_bit(14, CPM_SRBC);
udelay(300);
cpm_clear_bit(14, CPM_SRBC);
udelay(300);
has_reset = 1;
}
printk(KERN_DEBUG __FILE__
": Clock to USB host has been enabled \n");
return 0;
}
void jz_otg_phy_init(otg_mode_t mode)
{
unsigned int ref_clk_div = CONFIG_EXTAL_CLOCK / 24;
unsigned int usbpcr1, usbrdt;
/* select dwc otg */
cpm_set_bit(USBPCR1_USB_SEL, CPM_USBPCR1);
/* select utmi data bus width of port0 to 16bit/30M */
cpm_set_bit(USBPCR1_WORD_IF0, CPM_USBPCR1);
usbpcr1 = cpm_inl(CPM_USBPCR1);
usbpcr1 &= ~(0x3 << 24 | 1 << 30);
usbpcr1 |= (ref_clk_div << 24);
cpm_outl(usbpcr1, CPM_USBPCR1);
/*unsuspend*/
cpm_set_bit(7, CPM_OPCR);
udelay(45);
cpm_clear_bit(USBPCR_SIDDQ, CPM_USBPCR);
/* fil */
cpm_outl(0, CPM_USBVBFIL);
/* rdt */
usbrdt = cpm_inl(CPM_USBRDT);
usbrdt &= ~(USBRDT_VBFIL_LD_EN | ((1 << 23) - 1));
usbrdt |= 0x96;
cpm_outl(usbrdt, CPM_USBRDT);
/* rdt - filload_en */
cpm_set_bit(USBRDT_VBFIL_LD_EN, CPM_USBRDT);
/* TXRISETUNE & TXVREFTUNE. */
//cpm_outl(0x3f, CPM_USBPCR);
//cpm_outl(0x35, CPM_USBPCR);
/* enable tx pre-emphasis */
//cpm_set_bit(USBPCR_TXPREEMPHTUNE, CPM_USBPCR);
/* OTGTUNE adjust */
//cpm_outl(7 << 14, CPM_USBPCR);
cpm_outl(0x83803857, CPM_USBPCR);
if (mode == DEVICE_ONLY) {
pr_info("DWC IN DEVICE ONLY MODE\n");
cpm_clear_bit(USBPCR_USB_MODE, CPM_USBPCR);
cpm_clear_bit(USBPCR_OTG_DISABLE, CPM_USBPCR);
cpm_clear_bit(USBPCR_SIDDQ, CPM_USBPCR);
cpm_set_bit(USBPCR_COMMONONN, CPM_USBPCR);
} else {
unsigned int tmp;
pr_info("DWC IN OTG MODE\n");
tmp = cpm_inl(CPM_USBPCR);
tmp |= 1 << USBPCR_USB_MODE | 1 << USBPCR_COMMONONN;
tmp &= ~(1 << USBPCR_OTG_DISABLE | 1 << USBPCR_SIDDQ |
0x03 << USBPCR_IDPULLUP_MASK | 1 << USBPCR_VBUSVLDEXT |
1 << USBPCR_VBUSVLDEXTSEL);
cpm_outl(tmp, CPM_USBPCR);
}
cpm_set_bit(USBPCR_POR, CPM_USBPCR);
mdelay(1);
cpm_clear_bit(USBPCR_POR, CPM_USBPCR);
mdelay(1);
}