/* C entry point of secondary cpus */
asmlinkage void secondary_cpu_init(unsigned int index)
{
atomic_inc(&active_cpus);
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
spin_lock(&start_cpu_lock);
#ifdef __SSE3__
/*
* Seems that CR4 was cleared when AP start via lapic_start_cpu()
* Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
*/
u32 cr4_val;
cr4_val = read_cr4();
cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT);
write_cr4(cr4_val);
#endif
cpu_initialize(index);
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
spin_unlock(&start_cpu_lock);
atomic_dec(&active_cpus);
stop_this_cpu();
}
/*
* OS�̋N��
*/
void
StartOS(AppModeType mode)
{
volatile FP startuphook_adr;
LOG_STAOS_ENTER(mode);
/*
* �A�v���P�[�V�������[�h�̐ݒ�
*/
appmode = mode;
/*
* �^�[�Q�b�g�ˑ��̏�����
*/
cpu_initialize();
sys_initialize();
tool_initialize();
/*
* �e���W���[���̏�����
*/
object_initialize();
/*
* StartupHook �̌Ăяo��
*
* C�����̋K�i�ł͊��̃A�h���X��0�ɂȂ��Ȃ��Ƃ����O��,
* �R���p�C���̍œK���ɂ���StartupHook�̃A�h���X���蕪����
* �폜�����Ă��܂��ꍇ�����邽��, volatile�w�肵�����[�J���ϐ���
* �A�h���X���������Ă��画�肵�Ă����D
*
*/
startuphook_adr = (FP)StartupHook;
if (startuphook_adr != NULL) {
/*
* StartupHook �̒��ŁCSuspendAllInterrupts ���Ă�
* �Ă������v�Ȃ悤�ɁCsus_all_cnt �����[���ɂ��Ă����D
*/
callevel = TCL_STARTUP;
sus_all_cnt++;
StartupHook();
sus_all_cnt--;
}
callevel = TCL_TASK;
LOG_STAOS_LEAVE();
start_dispatch();
}
/*
* OSの起動
*/
void
StartOS(AppModeType mode)
{
volatile FP startuphook_adr;
LOG_STAOS_ENTER(mode);
/*
* アプリケーションモードの設定
*/
appmode = mode;
/*
* ターゲット依存の初期化
*/
cpu_initialize();
sys_initialize();
tool_initialize();
/*
* 各モジュールの初期化
*/
object_initialize();
/*
* StartupHook の呼び出し
*
* C言語の規格では関数のアドレスは0にならないという前提から,
* コンパイラの最適化によりStartupHookのアドレス判定分岐が
* 削除されてしまう場合があるため, volatile指定したローカル変数に
* アドレスを代入してから判定している．
*
*/
startuphook_adr = (FP)StartupHook;
if (startuphook_adr != NULL) {
/*
* StartupHook の中で，SuspendAllInterrupts が呼ばれ
* ても大丈夫なように，sus_all_cnt を非ゼロにしておく．
*/
callevel = TCL_STARTUP;
sus_all_cnt++;
StartupHook();
sus_all_cnt--;
}
callevel = TCL_TASK;
LOG_STAOS_LEAVE();
start_dispatch();
}
/*
* OS Start
*/
void
StartOS(AppModeType mode)
{
volatile FP startuphook_adr;
LOG_STAOS_ENTER(mode);
/*
* Store
*/
appmode = mode;
/*
* Do the needed initialize
*/
cpu_initialize(); /* implemented in cpu_context.c */
sys_initialize(); /* user defined interface */
tool_initialize(); /* user defined interface */
/*
* Initialize OSEK OS objects.
*/
object_initialize();
/*
* StartupHook の呼び出し
*
* C言語の規格では関数のアドレスは0にならないという前提から,
* コンパイラの最適化によりStartupHookのアドレス判定分岐が
* 削除されてしまう場合があるため, volatile指定したローカル変数に
* アドレスを代入してから判定している．
*
*/
startuphook_adr = (FP)StartupHook;
if (startuphook_adr != NULL) {
/*
* StartupHook の中で，SuspendAllInterrupts が呼ばれ
* ても大丈夫なように，sus_all_cnt を非ゼロにしておく．
*/
callevel = TCL_STARTUP;
sus_all_cnt++;
StartupHook();
sus_all_cnt--;
}
callevel = TCL_TASK;
LOG_STAOS_LEAVE();
start_dispatch();
}
/* This is the first C code that secondary processors invoke. */
void secondary_cpu_init(int cpuid, unsigned long r4)
{
struct vcpu *vcpu;
cpu_initialize(cpuid);
smp_generic_take_timebase();
/* If we are online, we must be able to ACK IPIs. */
mpic_setup_this_cpu();
cpu_set(cpuid, cpu_online_map);
vcpu = alloc_vcpu(idle_domain, cpuid, cpuid);
BUG_ON(vcpu == NULL);
set_current(idle_domain->vcpu[cpuid]);
idle_vcpu[cpuid] = current;
startup_cpu_idle_loop();
panic("should never get here\n");
}
int main(int argc, char *argv[]) {
Cpu cpu;
cpu_initialize(&cpu);
FILE *f = fopen(argv[1], "r");
fseek(f, 0, SEEK_END);
int sz = ftell(f);
fseek(f, 0, SEEK_SET);
byte *buffer = calloc(sz, sizeof(byte));
fread(buffer, 1, sz, f);
fclose(f);
while (cpu.pc < sz) {
cpu.pc += cpu_debugDecodeInstruction(&cpu, buffer);
}
return 0;
}
SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
bfd *abfd, char **argv)
{
SIM_DESC sd;
sim_cpu *cpu;
sd = sim_state_alloc (kind, callback);
cpu = STATE_CPU (sd, 0);
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
/* for compatibility */
current_alignment = NONSTRICT_ALIGNMENT;
current_target_byte_order = BIG_ENDIAN;
cpu_initialize (sd, cpu);
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
free_state (sd);
return 0;
}
/* Check for/establish the a reference program image. */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL), abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
free_state (sd);
return 0;
}
if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Fudge our descriptor. */
return sd;
}
static void __init __start_xen(void)
{
memcpy(0, exception_vectors, exception_vectors_end - exception_vectors);
synchronize_caches(0, exception_vectors_end - exception_vectors);
ticks_per_usec = timebase_freq / 1000000ULL;
/* Parse the command-line options. */
cmdline_parse(xen_cmdline);
/* we need to be able to identify this CPU early on */
init_boot_cpu();
/* We initialise the serial devices very early so we can get debugging. */
ns16550.io_base = 0x3f8;
ns16550_init(0, &ns16550);
ns16550.io_base = 0x2f8;
ns16550_init(1, &ns16550);
serial_init_preirq();
init_console();
console_start_sync(); /* Stay synchronous for early debugging. */
rtas_init((void *)oftree);
memory_init();
printk("xen_cmdline: %016lx\n", (ulong)xen_cmdline);
printk("dom0_cmdline: %016lx\n", (ulong)dom0_cmdline);
printk("dom0_addr: %016lx\n", (ulong)dom0_addr);
printk("dom0_len: %016lx\n", (ulong)dom0_len);
printk("initrd_start: %016lx\n", (ulong)initrd_start);
printk("initrd_len: %016lx\n", (ulong)initrd_len);
printk("dom0: %016llx\n", *(unsigned long long *)dom0_addr);
#ifdef OF_DEBUG
key_ofdump(0);
#endif
percpu_init_areas();
init_parea(0);
cpu_initialize(0);
#ifdef CONFIG_GDB
initialise_gdb();
if (opt_earlygdb)
debugger_trap_immediate();
#endif
start_of_day();
acm_init(NULL, 0);
mpic_setup_this_cpu();
/* Deal with secondary processors. */
if (opt_nosmp || ofd_boot_cpu == -1) {
printk("nosmp: leaving secondary processors spinning forever\n");
} else {
printk("spinning up at most %d total processors ...\n", max_cpus);
kick_secondary_cpus(max_cpus);
}
/* This cannot be called before secondary cpus are marked online. */
percpu_free_unused_areas();
/* Create initial domain 0. */
dom0 = domain_create(0, 0, DOM0_SSIDREF);
if (dom0 == NULL)
panic("Error creating domain 0\n");
/* The Interrupt Controller will route everything to CPU 0 so we
* need to make sure Dom0's vVCPU 0 is pinned to the CPU */
dom0->vcpu[0]->cpu_affinity = cpumask_of_cpu(0);
dom0->is_privileged = 1;
/* scrub_heap_pages() requires IRQs enabled, and we're post IRQ setup... */
local_irq_enable();
/* Scrub RAM that is still free and so may go to an unprivileged domain. */
scrub_heap_pages();
if ((dom0_addr == 0) || (dom0_len == 0))
panic("No domain 0 found.\n");
if (construct_dom0(dom0, dom0_addr, dom0_len,
initrd_start, initrd_len,
dom0_cmdline) != 0) {
panic("Could not set up DOM0 guest OS\n");
}
init_xenheap_pages(ALIGN_UP(dom0_addr, PAGE_SIZE),
ALIGN_DOWN(dom0_addr + dom0_len, PAGE_SIZE));
if (initrd_start)
init_xenheap_pages(ALIGN_UP(initrd_start, PAGE_SIZE),
ALIGN_DOWN(initrd_start + initrd_len, PAGE_SIZE));
init_trace_bufs();
console_endboot();
/* Hide UART from DOM0 if we're using it */
serial_endboot();
console_end_sync();
domain_unpause_by_systemcontroller(dom0);
#ifdef DEBUG_IPI
ipi_torture_test();
#endif
startup_cpu_idle_loop();
}
void initialize_cpus(struct bus *cpu_bus)
{
struct device_path cpu_path;
struct cpu_info *info;
/* Find the info struct for this CPU */
info = cpu_info();
if (need_lapic_init()) {
/* Ensure the local APIC is enabled */
enable_lapic();
/* Get the device path of the boot CPU */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = lapicid();
} else {
/* Get the device path of the boot CPU */
cpu_path.type = DEVICE_PATH_CPU;
cpu_path.cpu.id = 0;
}
/* Find the device structure for the boot CPU */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
// why here? In case some day we can start core1 in amd_sibling_init
if (is_smp_boot())
copy_secondary_start_to_lowest_1M();
if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
smm_init();
/* start all aps at first, so we can init ECC all together */
if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
/* Initialize the bootstrap processor */
cpu_initialize(0);
if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) {
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);
}
if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
/* At this point, all APs are sleeping:
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
smm_init();
if (is_smp_boot()) {
last_cpu_index = 0;
smm_other_cpus(cpu_bus, info->cpu);
}
}
smm_init_completion();
if (is_smp_boot())
recover_lowest_1M();
}
SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
bfd *abfd, char * const *argv)
{
int i;
SIM_DESC sd;
sim_cpu *cpu;
sd = sim_state_alloc (kind, callback);
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
cpu = STATE_CPU (sd, 0);
cpu_initialize (sd, cpu);
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
free_state (sd);
return 0;
}
/* Check for/establish the a reference program image. */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL), abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
free_state (sd);
return 0;
}
if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* CPU specific initialization. */
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
CPU_REG_STORE (cpu) = m68hc11_reg_store;
CPU_PC_FETCH (cpu) = m68hc11_pc_get;
CPU_PC_STORE (cpu) = m68hc11_pc_set;
}
return sd;
}
