static void
com_mace_attach(device_t parent, device_t self, void *aux)
{
struct com_mace_softc *msc = device_private(self);
struct com_softc *sc = &msc->sc_com;
struct mace_attach_args *maa = aux;
bus_space_handle_t ioh;
sc->sc_dev = self;
/*
* XXX should check com_is_console() and
* XXX use bus_space_map().
*/
ioh = maa->maa_sh + maa->maa_offset;
/* note that ioh on mac is *also* the iobase address */
COM_INIT_REGS(sc->sc_regs, maa->maa_st, ioh, ioh);
sc->sc_frequency = COM_FREQ;
delay(10000);
com_attach_subr(sc);
delay(10000);
cpu_intr_establish(maa->maa_intr, maa->maa_intrmask, comintr, sc);
return;
}
static void
sbwdog_attach(device_t parent, device_t self, void *aux)
{
struct sbwdog_softc *sc = device_private(self);
struct sbscd_attach_args *sa = aux;
sc->sc_dev = self;
sc->sc_wdog_period = SBWDOG_DEFAULT_PERIOD;
sc->sc_addr = MIPS_PHYS_TO_KSEG1(sa->sa_base + sa->sa_locs.sa_offset);
aprint_normal(": %d second period\n", sc->sc_wdog_period);
sc->sc_smw.smw_name = device_xname(sc->sc_dev);
sc->sc_smw.smw_cookie = sc;
sc->sc_smw.smw_setmode = sbwdog_setmode;
sc->sc_smw.smw_tickle = sbwdog_tickle;
sc->sc_smw.smw_period = sc->sc_wdog_period;
if (sysmon_wdog_register(&sc->sc_smw) != 0)
aprint_error_dev(self, "unable to register with sysmon\n");
if (sa->sa_locs.sa_intr[0] != SBOBIOCF_INTR_DEFAULT)
cpu_intr_establish(sa->sa_locs.sa_intr[0], IPL_HIGH,
sbwdog_intr, sc);
}
void *
pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
int (*func)(void *), void *arg)
{
if (ih >= NICU_INT)
return cpu_intr_establish(ih - NICU_INT, level, func, arg);
else
return icu_intr_establish(ih, IST_LEVEL, level, func, arg);
}
void
siop_sgc_attach(struct device *parent, struct device *self, void *aux)
{
struct siop_sgc_softc *sc = (struct siop_sgc_softc *)self;
struct confargs *ca = aux;
volatile struct iomod *regs;
sc->sc_iot = ca->ca_iot;
if (bus_space_map(sc->sc_iot, ca->ca_hpa,
IOMOD_HPASIZE, 0, &sc->sc_ioh)) {
printf(": cannot map io space\n");
return;
}
sc->sc_bustag = *sc->sc_iot;
sc->sc_bustag.hbt_r1 = siop_sgc_r1;
sc->sc_bustag.hbt_r2 = siop_sgc_r2;
sc->sc_bustag.hbt_w1 = siop_sgc_w1;
sc->sc_bustag.hbt_w2 = siop_sgc_w2;
sc->sc_siop.sc_c.features = SF_CHIP_PF | SF_CHIP_BE | SF_BUS_WIDE;
sc->sc_siop.sc_c.maxburst = 4;
sc->sc_siop.sc_c.maxoff = 8;
sc->sc_siop.sc_c.clock_div = 3;
sc->sc_siop.sc_c.clock_period = 250;
sc->sc_siop.sc_c.ram_size = 0;
sc->sc_siop.sc_c.sc_reset = siop_sgc_reset;
sc->sc_siop.sc_c.sc_dmat = ca->ca_dmatag;
sc->sc_siop.sc_c.sc_rt = &sc->sc_bustag;
bus_space_subregion(sc->sc_iot, sc->sc_ioh, IOMOD_DEVOFFSET,
IOMOD_HPASIZE - IOMOD_DEVOFFSET, &sc->sc_siop.sc_c.sc_rh);
regs = bus_space_vaddr(sc->sc_iot, sc->sc_ioh);
regs->io_command = CMD_RESET;
while ((regs->io_status & IO_ERR_MEM_RY) == 0)
delay(100);
regs->io_ii_rw = IO_II_PACKEN | IO_II_PREFETCHEN;
siop_sgc_reset(&sc->sc_siop.sc_c);
regs->io_eim = cpu_gethpa(0) | (31 - ca->ca_irq);
regs->io_ii_rw |= IO_II_INTEN;
cpu_intr_establish(IPL_BIO, ca->ca_irq, siop_intr, sc,
sc->sc_siop.sc_c.sc_dev.dv_xname);
printf(": NCR53C720 rev %d\n", bus_space_read_1(sc->sc_siop.sc_c.sc_rt,
sc->sc_siop.sc_c.sc_rh, SIOP_CTEST3) >> 4);
siop_attach(&sc->sc_siop);
}
void
com_mainbus_attach(device_t parent, device_t self, void *aux)
{
struct com_mainbus_softc *msc = device_private(self);
struct com_softc *sc = &msc->sc_com;
struct mainbus_attach_args *maa = aux;
bus_space_handle_t ioh;
sc->sc_dev = self;
if (!com_is_console(maa->ma_iot, maa->ma_addr, &ioh) &&
bus_space_map(maa->ma_iot, maa->ma_addr, COM_NPORTS, 0, &ioh)) {
aprint_error(": can't map i/o space\n");
return;
}
COM_INIT_REGS(sc->sc_regs, maa->ma_iot, ioh, maa->ma_addr);
sc->sc_frequency = COM_MAINBUS_FREQ;
com_attach_subr(sc);
cpu_intr_establish(maa->ma_level, IPL_SERIAL, comintr, sc);
return;
}
static void
macepci_attach(device_t parent, device_t self, void *aux)
{
struct macepci_softc *sc = device_private(self);
pci_chipset_tag_t pc = &sc->sc_pc;
struct mace_attach_args *maa = aux;
struct pcibus_attach_args pba;
u_int32_t control;
int rev;
if (bus_space_subregion(maa->maa_st, maa->maa_sh,
maa->maa_offset, 0, &pc->ioh) )
panic("macepci_attach: couldn't map");
pc->iot = maa->maa_st;
rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION);
printf(": rev %d\n", rev);
pc->pc_bus_maxdevs = macepci_bus_maxdevs;
pc->pc_conf_read = macepci_conf_read;
pc->pc_conf_write = macepci_conf_write;
pc->pc_intr_map = macepci_intr_map;
pc->pc_intr_string = macepci_intr_string;
pc->intr_establish = mace_intr_establish;
pc->intr_disestablish = mace_intr_disestablish;
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0);
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0);
/* Turn on PCI error interrupts */
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL,
MACE_PCI_CONTROL_SERR_ENA |
MACE_PCI_CONTROL_PARITY_ERR |
MACE_PCI_CONTROL_PARK_LIU |
MACE_PCI_CONTROL_OVERRUN_INT |
MACE_PCI_CONTROL_PARITY_INT |
MACE_PCI_CONTROL_SERR_INT |
MACE_PCI_CONTROL_IT_INT |
MACE_PCI_CONTROL_RE_INT |
MACE_PCI_CONTROL_DPED_INT |
MACE_PCI_CONTROL_TAR_INT |
MACE_PCI_CONTROL_MAR_INT);
/*
* Enable all MACE PCI interrupts. They will be masked by
* the CRIME code.
*/
control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL);
control |= CONTROL_INT_MASK;
bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
#if NPCI > 0
pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
NULL, 0, EX_NOWAIT);
pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
memset(&pba, 0, sizeof pba);
/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO;
/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
pba.pba_pc = pc;
#ifdef MACEPCI_IO_WAS_BUGGY
if (rev == 0)
pba.pba_flags &= ~PCI_FLAGS_IO_OKAY; /* Buggy? */
#endif
cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
static void
sq_attach(struct device *parent, struct device *self, void *aux)
{
int i, err;
char* macaddr;
struct sq_softc *sc = (void *)self;
struct hpc_attach_args *haa = aux;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
sc->sc_hpct = haa->ha_st;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_dmaoff,
HPC_ENET_REGS_SIZE,
&sc->sc_hpch)) != 0) {
printf(": unable to map HPC DMA registers, error = %d\n", err);
goto fail_0;
}
sc->sc_regt = haa->ha_st;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_devoff,
HPC_ENET_DEVREGS_SIZE,
&sc->sc_regh)) != 0) {
printf(": unable to map Seeq registers, error = %d\n", err);
goto fail_0;
}
sc->sc_dmat = haa->ha_dmat;
if ((err = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control),
PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg,
1, &sc->sc_ncdseg, BUS_DMA_NOWAIT)) != 0) {
printf(": unable to allocate control data, error = %d\n", err);
goto fail_0;
}
if ((err = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg,
sizeof(struct sq_control),
(caddr_t *)&sc->sc_control,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
printf(": unable to map control data, error = %d\n", err);
goto fail_1;
}
if ((err = bus_dmamap_create(sc->sc_dmat, sizeof(struct sq_control),
1, sizeof(struct sq_control), PAGE_SIZE,
BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) {
printf(": unable to create DMA map for control data, error "
"= %d\n", err);
goto fail_2;
}
if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap, sc->sc_control,
sizeof(struct sq_control),
NULL, BUS_DMA_NOWAIT)) != 0) {
printf(": unable to load DMA map for control data, error "
"= %d\n", err);
goto fail_3;
}
memset(sc->sc_control, 0, sizeof(struct sq_control));
/* Create transmit buffer DMA maps */
for (i = 0; i < SQ_NTXDESC; i++) {
if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
0, BUS_DMA_NOWAIT,
&sc->sc_txmap[i])) != 0) {
printf(": unable to create tx DMA map %d, error = %d\n",
i, err);
goto fail_4;
}
}
/* Create transmit buffer DMA maps */
for (i = 0; i < SQ_NRXDESC; i++) {
if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
0, BUS_DMA_NOWAIT,
&sc->sc_rxmap[i])) != 0) {
printf(": unable to create rx DMA map %d, error = %d\n",
i, err);
goto fail_5;
}
}
/* Pre-allocate the receive buffers. */
for (i = 0; i < SQ_NRXDESC; i++) {
if ((err = sq_add_rxbuf(sc, i)) != 0) {
printf(": unable to allocate or map rx buffer %d\n,"
" error = %d\n", i, err);
goto fail_6;
}
}
if ((macaddr = ARCBIOS->GetEnvironmentVariable("eaddr")) == NULL) {
printf(": unable to get MAC address!\n");
goto fail_6;
}
evcnt_attach_dynamic(&sc->sq_intrcnt, EVCNT_TYPE_INTR, NULL,
self->dv_xname, "intr");
if ((cpu_intr_establish(haa->ha_irq, IPL_NET, sq_intr, sc)) == NULL) {
printf(": unable to establish interrupt!\n");
goto fail_6;
}
/* Reset the chip to a known state. */
sq_reset(sc);
/*
* Determine if we're an 8003 or 80c03 by setting the first
* MAC address register to non-zero, and then reading it back.
* If it's zero, we have an 80c03, because we will have read
* the TxCollLSB register.
*/
bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCOLLS0, 0xa5);
if (bus_space_read_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCOLLS0) == 0)
sc->sc_type = SQ_TYPE_80C03;
else
sc->sc_type = SQ_TYPE_8003;
bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCOLLS0, 0x00);
printf(": SGI Seeq %s\n",
sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003");
enaddr_aton(macaddr, sc->sc_enaddr);
printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
ether_sprintf(sc->sc_enaddr));
strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
ifp->if_softc = sc;
ifp->if_mtu = ETHERMTU;
ifp->if_init = sq_init;
ifp->if_stop = sq_stop;
ifp->if_start = sq_start;
ifp->if_ioctl = sq_ioctl;
ifp->if_watchdog = sq_watchdog;
ifp->if_flags = IFF_BROADCAST | IFF_NOTRAILERS | IFF_MULTICAST;
IFQ_SET_READY(&ifp->if_snd);
if_attach(ifp);
ether_ifattach(ifp, sc->sc_enaddr);
memset(&sq_trace, 0, sizeof(sq_trace));
/* Done! */
return;
/*
* Free any resources we've allocated during the failed attach
* attempt. Do this in reverse order and fall through.
*/
fail_6:
for (i = 0; i < SQ_NRXDESC; i++) {
if (sc->sc_rxmbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]);
m_freem(sc->sc_rxmbuf[i]);
}
}
fail_5:
for (i = 0; i < SQ_NRXDESC; i++) {
if (sc->sc_rxmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]);
}
fail_4:
for (i = 0; i < SQ_NTXDESC; i++) {
if (sc->sc_txmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]);
}
bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap);
fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap);
fail_2:
bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_control,
sizeof(struct sq_control));
fail_1:
bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg);
fail_0:
return;
}
void *
apic_intr_establish(void *v, pci_intr_handle_t ih,
int pri, int (*handler)(void *), void *arg, const char *name)
{
struct elroy_softc *sc = v;
volatile struct elroy_regs *r = sc->sc_regs;
hppa_hpa_t hpa = cpu_gethpa(0);
struct evcount *cnt;
struct apic_iv *aiv, *biv;
void *iv;
int irq = APIC_INT_IRQ(ih);
int line = APIC_INT_LINE(ih);
u_int32_t ent0;
/* no mapping or bogus */
if (irq <= 0 || irq > 63)
return (NULL);
aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_NOWAIT);
if (aiv == NULL) {
free(cnt, M_DEVBUF, 0);
return NULL;
}
aiv->sc = sc;
aiv->ih = ih;
aiv->handler = handler;
aiv->arg = arg;
aiv->next = NULL;
aiv->cnt = NULL;
if (apic_intr_list[irq]) {
cnt = malloc(sizeof(struct evcount), M_DEVBUF, M_NOWAIT);
if (!cnt) {
free(aiv, M_DEVBUF, 0);
return (NULL);
}
evcount_attach(cnt, name, NULL);
biv = apic_intr_list[irq];
while (biv->next)
biv = biv->next;
biv->next = aiv;
aiv->cnt = cnt;
return (arg);
}
if ((iv = cpu_intr_establish(pri, irq, apic_intr, aiv, name))) {
ent0 = (63 - irq) & APIC_ENT0_VEC;
ent0 |= apic_get_int_ent0(sc, line);
#if 0
if (cold) {
sc->sc_imr |= (1 << irq);
ent0 |= APIC_ENT0_MASK;
}
#endif
apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
apic_write(sc->sc_regs, APIC_ENT1(line),
((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
/* Signal EOI. */
elroy_write32(&r->apic_eoi,
htole32((63 - irq) & APIC_ENT0_VEC));
apic_intr_list[irq] = aiv;
}
/*
* Attach a found zs.
*
* Match slave number to zs unit number, so that misconfiguration will
* not set up the keyboard as ttya, etc.
*/
static void
zs_hpc_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct hpc_attach_args *haa = aux;
struct zsc_attach_args zsc_args;
struct zs_chanstate *cs;
struct zs_channel *ch;
int zs_unit, channel, err, s;
const char *promconsdev;
promconsdev = arcbios_GetEnvironmentVariable("ConsoleOut");
zsc->zsc_dev = self;
zsc->zsc_bustag = haa->ha_st;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_devoff, 0x10,
&zsc->zsc_base)) != 0) {
aprint_error(": unable to map 85c30 registers, error = %d\n",
err);
return;
}
zs_unit = device_unit(self);
aprint_normal("\n");
/*
* Initialize software state for each channel.
*
* Done in reverse order of channels since the first serial port
* is actually attached to the *second* channel, and vice versa.
* Doing it this way should force a 'zstty*' to attach zstty0 to
* channel 1 and zstty1 to channel 0. They couldn't have wired
* it up in a more sensible fashion, could they?
*/
for (channel = 1; channel >= 0; channel--) {
zsc_args.channel = channel;
ch = &zsc->zsc_cs_store[channel];
cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
zs_lock_init(cs);
cs->cs_reg_csr = NULL;
cs->cs_reg_data = NULL;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base,
zs_chan_offset[channel],
sizeof(struct zschan),
&ch->cs_regs) != 0) {
aprint_error_dev(self, "cannot map regs\n");
return;
}
ch->cs_bustag = zsc->zsc_bustag;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
zsc_args.hwflags = 0;
zsc_args.consdev = NULL;
if (zs_consunit == -1 && zs_conschan == -1) {
/*
* If this channel is being used by the PROM console,
* pass the generic zs driver a 'no reset' flag so the
* channel gets left in the appropriate state after
* attach.
*
* Note: the channel mappings are swapped.
*/
if (promconsdev != NULL &&
strlen(promconsdev) == 9 &&
strncmp(promconsdev, "serial", 6) == 0 &&
(promconsdev[7] == '0' || promconsdev[7] == '1')) {
if (promconsdev[7] == '1' && channel == 0)
zsc_args.hwflags |= ZS_HWFLAG_NORESET;
else if (promconsdev[7] == '0' && channel == 1)
zsc_args.hwflags |= ZS_HWFLAG_NORESET;
}
}
/* If console, don't stomp speed, let zstty know */
if (zs_unit == zs_consunit && channel == zs_conschan) {
zsc_args.consdev = &zs_cn;
zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
cs->cs_defspeed = zs_get_speed(cs);
} else
cs->cs_defspeed = zs_defspeed;
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL);
evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
static void
sq_attach(device_t parent, device_t self, void *aux)
{
int i, err;
const char* macaddr;
struct sq_softc *sc = device_private(self);
struct hpc_attach_args *haa = aux;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
sc->sc_dev = self;
sc->sc_hpct = haa->ha_st;
sc->hpc_regs = haa->hpc_regs; /* HPC register definitions */
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_dmaoff, sc->hpc_regs->enet_regs_size,
&sc->sc_hpch)) != 0) {
printf(": unable to map HPC DMA registers, error = %d\n", err);
goto fail_0;
}
sc->sc_regt = haa->ha_st;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_devoff, sc->hpc_regs->enet_devregs_size,
&sc->sc_regh)) != 0) {
printf(": unable to map Seeq registers, error = %d\n", err);
goto fail_0;
}
sc->sc_dmat = haa->ha_dmat;
if ((err = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control),
PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg, 1, &sc->sc_ncdseg,
BUS_DMA_NOWAIT)) != 0) {
printf(": unable to allocate control data, error = %d\n", err);
goto fail_0;
}
if ((err = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg,
sizeof(struct sq_control), (void **)&sc->sc_control,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
printf(": unable to map control data, error = %d\n", err);
goto fail_1;
}
if ((err = bus_dmamap_create(sc->sc_dmat,
sizeof(struct sq_control), 1, sizeof(struct sq_control), PAGE_SIZE,
BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) {
printf(": unable to create DMA map for control data, error "
"= %d\n", err);
goto fail_2;
}
if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap,
sc->sc_control, sizeof(struct sq_control), NULL,
BUS_DMA_NOWAIT)) != 0) {
printf(": unable to load DMA map for control data, error "
"= %d\n", err);
goto fail_3;
}
memset(sc->sc_control, 0, sizeof(struct sq_control));
/* Create transmit buffer DMA maps */
for (i = 0; i < SQ_NTXDESC; i++) {
if ((err = bus_dmamap_create(sc->sc_dmat,
MCLBYTES, 1, MCLBYTES, 0,
BUS_DMA_NOWAIT, &sc->sc_txmap[i])) != 0) {
printf(": unable to create tx DMA map %d, error = %d\n",
i, err);
goto fail_4;
}
}
/* Create receive buffer DMA maps */
for (i = 0; i < SQ_NRXDESC; i++) {
if ((err = bus_dmamap_create(sc->sc_dmat,
MCLBYTES, 1, MCLBYTES, 0,
BUS_DMA_NOWAIT, &sc->sc_rxmap[i])) != 0) {
printf(": unable to create rx DMA map %d, error = %d\n",
i, err);
goto fail_5;
}
}
/* Pre-allocate the receive buffers. */
for (i = 0; i < SQ_NRXDESC; i++) {
if ((err = sq_add_rxbuf(sc, i)) != 0) {
printf(": unable to allocate or map rx buffer %d\n,"
" error = %d\n", i, err);
goto fail_6;
}
}
memcpy(sc->sc_enaddr, &haa->hpc_eeprom[SQ_HPC_EEPROM_ENADDR],
ETHER_ADDR_LEN);
/*
* If our mac address is bogus, obtain it from ARCBIOS. This will
* be true of the onboard HPC3 on IP22, since there is no eeprom,
* but rather the DS1386 RTC's battery-backed ram is used.
*/
if (sc->sc_enaddr[0] != SGI_OUI_0 ||
sc->sc_enaddr[1] != SGI_OUI_1 ||
sc->sc_enaddr[2] != SGI_OUI_2) {
macaddr = arcbios_GetEnvironmentVariable("eaddr");
if (macaddr == NULL) {
printf(": unable to get MAC address!\n");
goto fail_6;
}
ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr);
}
evcnt_attach_dynamic(&sc->sq_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
if ((cpu_intr_establish(haa->ha_irq, IPL_NET, sq_intr, sc)) == NULL) {
printf(": unable to establish interrupt!\n");
goto fail_6;
}
/* Reset the chip to a known state. */
sq_reset(sc);
/*
* Determine if we're an 8003 or 80c03 by setting the first
* MAC address register to non-zero, and then reading it back.
* If it's zero, we have an 80c03, because we will have read
* the TxCollLSB register.
*/
sq_seeq_write(sc, SEEQ_TXCOLLS0, 0xa5);
if (sq_seeq_read(sc, SEEQ_TXCOLLS0) == 0)
sc->sc_type = SQ_TYPE_80C03;
else
sc->sc_type = SQ_TYPE_8003;
sq_seeq_write(sc, SEEQ_TXCOLLS0, 0x00);
printf(": SGI Seeq %s\n",
sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003");
printf("%s: Ethernet address %s\n",
device_xname(self), ether_sprintf(sc->sc_enaddr));
strcpy(ifp->if_xname, device_xname(self));
ifp->if_softc = sc;
ifp->if_mtu = ETHERMTU;
ifp->if_init = sq_init;
ifp->if_stop = sq_stop;
ifp->if_start = sq_start;
ifp->if_ioctl = sq_ioctl;
ifp->if_watchdog = sq_watchdog;
ifp->if_flags = IFF_BROADCAST | IFF_NOTRAILERS | IFF_MULTICAST;
IFQ_SET_READY(&ifp->if_snd);
if_attach(ifp);
ether_ifattach(ifp, sc->sc_enaddr);
memset(&sc->sq_trace, 0, sizeof(sc->sq_trace));
/* Done! */
return;
/*
* Free any resources we've allocated during the failed attach
* attempt. Do this in reverse order and fall through.
*/
fail_6:
for (i = 0; i < SQ_NRXDESC; i++) {
if (sc->sc_rxmbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]);
m_freem(sc->sc_rxmbuf[i]);
}
}
fail_5:
for (i = 0; i < SQ_NRXDESC; i++) {
if (sc->sc_rxmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]);
}
fail_4:
for (i = 0; i < SQ_NTXDESC; i++) {
if (sc->sc_txmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]);
}
bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap);
fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap);
fail_2:
bus_dmamem_unmap(sc->sc_dmat,
(void *)sc->sc_control, sizeof(struct sq_control));
fail_1:
bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg);
fail_0:
return;
}
void
sbscn_attach_channel(struct sbscn_softc *sc, int chan, int intr)
{
struct sbscn_channel *ch = &sc->sc_channels[chan];
u_long chan_addr;
struct tty *tp;
ch->ch_sc = sc;
ch->ch_num = chan;
chan_addr = sc->sc_addr + (0x100 * chan);
ch->ch_base = (void *)MIPS_PHYS_TO_KSEG1(chan_addr);
ch->ch_isr_base =
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x220 + (0x20 * chan));
ch->ch_imr_base =
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x230 + (0x20 * chan));
#ifdef XXXCGDnotyet
ch->ch_inchg_base =
(void *)MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x2d0 + (0x10 * chan));
#endif
ch->ch_i_dcd = ch->ch_i_dcd_pin = 0 /* XXXCGD */;
ch->ch_i_cts = ch->ch_i_cts_pin = 0 /* XXXCGD */;
ch->ch_i_dsr = ch->ch_i_dsr_pin = 0 /* XXXCGD */;
ch->ch_i_ri = ch->ch_i_ri_pin = 0 /* XXXCGD */;
ch->ch_i_mask =
ch->ch_i_dcd | ch->ch_i_cts | ch->ch_i_dsr | ch->ch_i_ri;
ch->ch_o_dtr = ch->ch_o_dtr_pin = 0 /* XXXCGD */;
ch->ch_o_rts = ch->ch_o_rts_pin = 0 /* XXXCGD */;
ch->ch_o_mask = ch->ch_o_dtr | ch->ch_o_rts;
ch->ch_intrhand = cpu_intr_establish(intr, IPL_SERIAL, sbscn_intr, ch);
callout_init(&ch->ch_diag_callout, 0);
/* Disable interrupts before configuring the device. */
ch->ch_imr = 0;
WRITE_REG(ch->ch_imr_base, ch->ch_imr);
if (sbscn_cons_present &&
sbscn_cons_addr == chan_addr && sbscn_cons_chan == chan) {
sbscn_cons_attached = 1;
/* Make sure the console is always "hardwired". */
delay(1000); /* wait for output to finish */
SET(ch->ch_hwflags, SBSCN_HW_CONSOLE);
SET(ch->ch_swflags, TIOCFLAG_SOFTCAR);
}
tp = tty_alloc();
tp->t_oproc = sbscn_start;
tp->t_param = sbscn_param;
tp->t_hwiflow = sbscn_hwiflow;
ch->ch_tty = tp;
ch->ch_rbuf = malloc(sbscn_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
if (ch->ch_rbuf == NULL) {
aprint_error_dev(sc->sc_dev,
"channel %d: unable to allocate ring buffer\n",
chan);
return;
}
ch->ch_ebuf = ch->ch_rbuf + (sbscn_rbuf_size << 1);
tty_attach(tp);
if (ISSET(ch->ch_hwflags, SBSCN_HW_CONSOLE)) {
int maj;
/* locate the major number */
maj = cdevsw_lookup_major(&sbscn_cdevsw);
cn_tab->cn_dev = makedev(maj,
(device_unit(sc->sc_dev) << 1) + chan);
aprint_normal_dev(sc->sc_dev, "channel %d: %s\n",
chan, "console");
}
#ifdef KGDB
/*
* Allow kgdb to "take over" this port. If this is
* the kgdb device, it has exclusive use.
*/
if (sbscn_kgdb_present &&
sbscn_kgdb_addr == chan_addr && sbscn_kgdb_chan == chan) {
sbscn_kgdb_attached = 1;
SET(sc->sc_hwflags, SBSCN_HW_KGDB);
aprint_normal_dev(sc->sc_dev, "channel %d: %s\n",
chan, "kgdb");
}
#endif
ch->ch_si = softint_establish(SOFTINT_SERIAL, sbscn_soft, ch);
#ifdef RND_SBSCN
rnd_attach_source(&ch->ch_rnd_source, device_xname(sc->sc_dev),
RND_TYPE_TTY, 0);
#endif
sbscn_config(ch);
SET(ch->ch_hwflags, SBSCN_HW_DEV_OK);
}
