static inline void phy_on(void)
{
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
/* power everything up; start the on-chip PHY and its PLL */
phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
if (cpu_is_davinci_dm646x()) {
phy_ctrl |= USBPHY_NDATAPOL | USBPHY_SESSION_VBUS;
phy_ctrl |= is_peripheral_enabled() ? USBPHY_PERI_USBID :
phy_ctrl;
phy_ctrl &= ~USBPHY_VBDTCTEN;
}
if (cpu_is_davinci_dm365()) {
/*
* DM365 PHYCLKFREQ field [15:12] is set to 2
* to get clock from 24MHz crystal
*/
phy_ctrl |= USBPHY_CLKFREQ_24MHZ;
/*phy_ctrl &= ~USBPHY_PHYPDWN;*/
}
__raw_writel(phy_ctrl, USB_PHY_CTRL);
/* wait for PLL to lock before proceeding */
while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
cpu_relax();
}
/* dm646x_pci_init
* PCI system initialization. Fills in required information for PCI BIOS to
* perrform enumeratios and invokes pci_common_init.
*/
static int __init dm646x_pci_init(void)
{
if (cpu_is_davinci_dm646x()) {
/* Since DM646x can act either as PCI host or target, we skip
* setting up PCI BIOS for enumeration if we are 'target'.
* This is determined by checking BOOTCFG BOOTMODE[0:3] and
* PCIEN values.
* Note : BOOTCFG values are latched across soft resets and thus
* the check below cannot detect any change in actual boot mode.
*/
u32 bootcfg = __raw_readl(
(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE)
+ BOOTCFG));
u32 bootmode = bootcfg & 0xf;
pr_info("PCI: bootcfg = %#x, bootmode = %#x\n",
bootcfg, bootmode);
if (!((bootcfg & BIT(16))
&& ((bootmode == 2) || (bootmode == 3)))) {
pr_info("PCI: Invoking PCI BIOS...\n");
pci_common_init(&davinci_pci);
} else {
pr_info("PCI: Skipping PCI Host setup...\n");
}
}
return 0;
}
static int __init dm646x_init_devices(void)
{
if (!cpu_is_davinci_dm646x())
return 0;
platform_device_register(&dm646x_edma_device);
platform_device_register(&dm646x_emac_device);
return 0;
}
static int __init dm646x_init_devices(void)
{
if (!cpu_is_davinci_dm646x())
return 0;
platform_device_register(&dm646x_mdio_device);
platform_device_register(&dm646x_emac_device);
clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
NULL, &dm646x_emac_device.dev);
return 0;
}
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
unsigned i;
if (cpu_is_davinci_dm644x())
davinci_def_priorities = dm644x_default_priorities;
else if (cpu_is_davinci_dm646x())
davinci_def_priorities = dm646x_default_priorities;
else if (cpu_is_davinci_dm355())
davinci_def_priorities = dm355_default_priorities;
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
/* Disable all interrupts */
davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
/* Interrupts disabled immediately, IRQ entry reflects all */
davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
/* we don't use the hardware vector table, just its entry addresses */
davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
unsigned j;
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
pri |= (*davinci_def_priorities & 0x07) << j;
davinci_irq_writel(pri, i);
}
/* set up genirq dispatch for ARM INTC */
for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
set_irq_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (i != IRQ_TINT1_TINT34)
set_irq_handler(i, handle_edge_irq);
else
set_irq_handler(i, handle_level_irq);
}
}
void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
{
usb_data.power = mA > 510 ? 255 : mA / 2;
usb_data.potpgt = (potpgt_ms + 1) / 2;
if (cpu_is_davinci_dm646x()) {
/* Override the defaults as DM6467 uses different IRQs. */
usb_dev.resource[1].start = IRQ_DM646X_USBINT;
usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT;
} else /* other devices don't have dedicated CPPI IRQ */
usb_dev.num_resources = 2;
platform_device_register(&usb_dev);
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
* for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
*
* FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
* not handled right here ...
*/
switch (module) {
case 1:
if (cpu_is_davinci_dm365()) {
void __iomem *pupdctl1 =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
/* Configure pull down control */
__raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
pupdctl1);
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
void __init setup_usb(unsigned mA, unsigned potpgt_msec)
{
usb_data.power = mA / 2;
usb_data.potpgt = potpgt_msec / 2;
if (cpu_is_davinci_dm646x()) {
usb_dev.resource[1].start = IRQ_DM646X_USBINT;
usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT;
} else
usb_dev.num_resources = 2;
platform_device_register(&usb_dev);
}
void __init davinci_init_ide(void)
{
if (cpu_is_davinci_dm644x()) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN);
davinci_cfg_reg(DM644X_HDIREN);
} else if (cpu_is_davinci_dm646x()) {
/* IRQ_DM646X_IDE is the same as IRQ_IDE */
davinci_cfg_reg(DM646X_ATAEN);
} else {
WARN_ON(1);
return;
}
platform_device_register(&ide_device);
}
static int __init dm646x_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm646x())
return 0;
platform_device_register(&dm646x_mdio_device);
platform_device_register(&dm646x_emac_device);
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
static void __init davinci_serial_reset(struct plat_serial8250_port *p)
{
unsigned int pwremu = 0;
serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
/* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
mdelay(10);
pwremu |= (0x3 << 13);
pwremu |= 0x1;
serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
if (cpu_is_davinci_dm646x())
serial_write_reg(p, UART_DM646X_SCR,
UART_DM646X_SCR_TX_WATERMARK);
}
static void __init davinci_serial_reset(struct plat_serial8250_port *p)
{
unsigned int pwremu = 0;
serial_write_reg(p, UART_IER, 0);
serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
mdelay(10);
pwremu |= (0x3 << 13);
pwremu |= 0x1;
serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
if (cpu_is_davinci_dm646x())
serial_write_reg(p, UART_DM646X_SCR,
UART_DM646X_SCR_TX_WATERMARK);
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
* for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
*
* FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
* not handled right here ...
*/
switch (module) {
case 1:
if (cpu_is_davinci_dm355()) {
/* REVISIT we may not need all these pins if e.g. this
* is a hard-wired SDIO device...
*/
davinci_cfg_reg(DM355_SD1_CMD);
davinci_cfg_reg(DM355_SD1_CLK);
davinci_cfg_reg(DM355_SD1_DATA0);
davinci_cfg_reg(DM355_SD1_DATA1);
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
/* Configure pull down control */
unsigned v;
v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
__raw_writel(v & ~0xfc0,
DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
davinci_mmcsd1_device.name = "da830-mmc";
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
/* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
davinci_cfg_reg(DM355_MMCSD0);
/* enable RX EDMA */
davinci_cfg_reg(DM355_EVT26_MMC0_RX);
} else if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
davinci_mmcsd0_device.name = "da830-mmc";
} else if (cpu_is_davinci_dm644x()) {
/* REVISIT: should this be in board-init code? */
/* Power-on 3.3V IO cells */
__raw_writel(0,
DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
/*Set up the pull regiter for MMC */
davinci_cfg_reg(DM644X_MSTK);
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
switch (module) {
case 1:
if (cpu_is_davinci_dm355()) {
davinci_cfg_reg(DM355_SD1_CMD);
davinci_cfg_reg(DM355_SD1_CLK);
davinci_cfg_reg(DM355_SD1_DATA0);
davinci_cfg_reg(DM355_SD1_DATA1);
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
void __iomem *pupdctl1 =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
__raw_writel((__raw_readl(pupdctl1) & ~0x400),
pupdctl1);
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1;
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
davinci_cfg_reg(DM355_MMCSD0);
davinci_cfg_reg(DM355_EVT26_MMC0_RX);
} else if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
} else if (cpu_is_davinci_dm644x()) {
void __iomem *base =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
__raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
davinci_cfg_reg(DM644X_MSTK);
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
