static void gpt_irq_acknowledge(void) { if (cpu_is_mx1()) __raw_writel(0, timer_base + MX1_2_TSTAT); if (cpu_is_mx2()) __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); if (cpu_is_mx3() || cpu_is_mx25()) __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); }
void __init mxc_timer_init(struct clk *timer_clk) { uint32_t tctl_val; int irq; clk_enable(timer_clk); if (cpu_is_mx1()) { #ifdef CONFIG_ARCH_MX1 timer_base = IO_ADDRESS(TIM1_BASE_ADDR); irq = TIM1_INT; #endif } else if (cpu_is_mx2()) { #ifdef CONFIG_ARCH_MX2 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT1; #endif } else if (cpu_is_mx3()) { #ifdef CONFIG_ARCH_MX3 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT; #endif } else BUG(); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (cpu_is_mx3()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }