int __init omap_twl4030_init(void)
{
/* Reuse OMAP3430 values */
if (cpu_is_omap3630()) {
omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
if (cpu_is_omap446x()) {
/* use SMPS1 for CORE instead of SMPS3 on 4430 */
omap_twl_map[1].pmic_data->volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG;
omap_twl_map[1].pmic_data->cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG;
/* Adjust min / max voltages */
omap_twl_map[0].pmic_data->vp_vddmin = OMAP4460_VP_MPU_VLIMITTO_VDDMIN;
omap_twl_map[0].pmic_data->vp_vddmax = OMAP4460_VP_MPU_VLIMITTO_VDDMAX;
omap_twl_map[1].pmic_data->vp_vddmin = OMAP4460_VP_CORE_VLIMITTO_VDDMIN;
omap_twl_map[1].pmic_data->vp_vddmax = OMAP4460_VP_CORE_VLIMITTO_VDDMAX;
omap_twl_map[2].pmic_data->vp_vddmin = OMAP4460_VP_IVA_VLIMITTO_VDDMIN;
omap_twl_map[2].pmic_data->vp_vddmax = OMAP4460_VP_IVA_VLIMITTO_VDDMAX;
}
if (cpu_is_omap34xx())
return omap_pmic_register_data(omap3_twl_map);
else if (cpu_is_omap443x())
return omap_pmic_register_data(&omap_twl_map[0]);
else if (cpu_is_omap446x()) /* mpu from tps6236x */
return omap_pmic_register_data(&omap_twl_map[1]);
else
return 0;
}
static void __init omap4_panda_init(void)
{
int package = OMAP_PACKAGE_CBS;
int ret;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap_emif_set_device_details(1, &lpddr2_elpida_2G_S4_x2_info,
lpddr2_elpida_2G_S4_timings,
ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
&lpddr2_elpida_S4_min_tck,
&custom_configs);
omap_emif_set_device_details(2, &lpddr2_elpida_2G_S4_x2_info,
lpddr2_elpida_2G_S4_timings,
ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
&lpddr2_elpida_S4_min_tck,
&custom_configs);
if (cpu_is_omap446x())
gpio_leds[0].gpio = 110;
omap4_mux_init(board_mux, NULL, package);
omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
omap_register_mac_device_fixup_paths(panda_fixup_mac_device_paths,
ARRAY_SIZE(panda_fixup_mac_device_paths));
ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
if (ret)
pr_err("error setting wl12xx data: %d\n", ret);
omap4_panda_init_rev();
omap4_panda_i2c_init();
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
platform_device_register(&omap_vwlan_device);
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
usb_musb_init(&musb_board_data);
omap4_panda_display_init();
#ifdef CONFIG_MACH_OMAP4_PANDA_CAMERA_SUPPORT
panda_camera_init(&panda_camera_board_info);
#endif
if (cpu_is_omap446x()) {
/* Vsel0 = gpio, vsel1 = gnd */
ret = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
OMAP_PIN_OFF_OUTPUT_HIGH, -1);
if (ret)
pr_err("TPS62361 initialization failed: %d\n", ret);
}
omap_enable_smartreflex_on_init();
}
void __init omap44xx_voltagedomains_init(void)
{
struct voltagedomain *voltdm;
int i;
/*
* XXX Will depend on the process, validation, and binning
* for the currently-running IC
*/
#ifdef CONFIG_PM_OPP
if (cpu_is_omap443x()) {
omap4_voltdm_mpu.volt_data = omap443x_vdd_mpu_volt_data;
omap4_voltdm_iva.volt_data = omap443x_vdd_iva_volt_data;
omap4_voltdm_core.volt_data = omap443x_vdd_core_volt_data;
} else if (cpu_is_omap446x()) {
omap4_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
omap4_voltdm_iva.volt_data = omap446x_vdd_iva_volt_data;
omap4_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
}
#endif
omap4_voltdm_mpu.vp_param = &omap4_mpu_vp_data;
omap4_voltdm_iva.vp_param = &omap4_iva_vp_data;
omap4_voltdm_core.vp_param = &omap4_core_vp_data;
omap4_voltdm_mpu.vc_param = &omap4_mpu_vc_data;
omap4_voltdm_iva.vc_param = &omap4_iva_vc_data;
omap4_voltdm_core.vc_param = &omap4_core_vc_data;
for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;
voltdm_init(voltagedomains_omap4);
};
/**
* omap4_opp_init() - initialize omap4 opp table
*/
int __init omap4_opp_init(void)
{
int r = -ENODEV;
int trimmed = 1;
if (!cpu_is_omap44xx())
return r;
if (cpu_is_omap443x())
r = omap_init_opp_table(omap443x_opp_def_list,
ARRAY_SIZE(omap443x_opp_def_list));
else if (cpu_is_omap446x()) {
r = omap_init_opp_table(omap446x_opp_def_list,
ARRAY_SIZE(omap446x_opp_def_list));
trimmed = omap_readl(0x4a002268) & ((1 << 18) | (1 << 19));
/* if device is untrimmed override DPLL TRIM register */
if (!trimmed)
omap_writel(0x29, 0x4a002330);
}
if (!r) {
if (omap4_has_mpu_1_2ghz())
omap4_mpu_opp_enable(1200000000);
if (!trimmed)
pr_info("This is DPLL un-trimmed SOM. OPP is limited at 1.2 GHz\n");
if (omap4_has_mpu_1_5ghz() && trimmed)
omap4_mpu_opp_enable(1500000000);
}
return r;
}
/**
* omap4_opp_init() - initialize omap4 opp table
*/
int __init omap4_opp_init(void)
{
int r = -ENODEV;
if (!cpu_is_omap44xx())
return r;
if (cpu_is_omap443x())
r = omap_init_opp_table(omap443x_opp_def_list,
ARRAY_SIZE(omap443x_opp_def_list));
else if (cpu_is_omap446x())
r = omap_init_opp_table(omap446x_opp_def_list,
ARRAY_SIZE(omap446x_opp_def_list));
if (!r) {
if (omap4_has_mpu_1_2ghz())
omap4_mpu_opp_enable(1200000000);
/* 1.8Ghz까지 오버클럭 */
if (omap4_has_mpu_1_5ghz())
omap4_mpu_opp_enable(1340000000);
omap4_mpu_opp_enable(1520000000);
omap4_mpu_opp_enable(1650000000);
}
return r;
}
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
{
void *startup_addr = omap4_secondary_startup;
void __iomem *base = omap_get_wakeupgen_base();
/*
* Initialise the SCU and wake up the secondary core using
* wakeup_secondary().
*/
if (scu_base)
scu_enable(scu_base);
if (cpu_is_omap446x()) {
startup_addr = omap4460_secondary_startup;
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
}
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
}
static void __init omap_4430sdp_display_init(void)
{
int r;
/* Enable LCD2 by default (instead of Pico DLP) */
r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
"display_sel");
if (r)
pr_err("%s: Could not get display_sel GPIO\n", __func__);
sdp4430_picodlp_init();
omap_display_init(&sdp4430_dss_data);
/*
* OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
* later have external pull up on the HDMI I2C lines
*/
if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
else
omap_hdmi_init(0);
omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
}
static void __init wakeup_secondary(void)
{
void *startup_addr = omap_secondary_startup;
void __iomem *base = omap_get_wakeupgen_base();
if (cpu_is_omap446x()) {
startup_addr = omap_secondary_startup_4460;
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
}
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
smp_wmb();
/*
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb_sev();
mb();
}
int __init pcb_temp_sensor_init(void)
{
if (!cpu_is_omap446x())
return 0;
return platform_driver_register(&pcb_temp_sensor_driver);
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
u32 diag0_errata_flags = 0;
/* Enable NS access to SMP bit for this CPU on HS devices */
if (cpu_is_omap446x() || cpu_is_omap443x()) {
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
omap4_secure_dispatcher(PPA_SERVICE_DEFAULT_POR_NS_SMP,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
else {
diag0_errata_flags =
omap4_get_diagctrl0_errata_flags();
if (diag0_errata_flags)
omap_smc1(HAL_DIAGREG_0, diag0_errata_flags);
}
}
/*
* If any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
/*
* omap4_sar_save -
* Save the context to SAR_RAM1 and SAR_RAM2 as per
* omap4xxx_sar_ram1_layout and omap4xxx_sar_ram2_layout for the device OFF
* mode
*/
int omap4_sar_save(void)
{
/*
* Not supported on ES1.0 silicon
*/
if (omap_rev() == OMAP4430_REV_ES1_0) {
WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n");
return -ENODEV;
}
if (omap4_sar_not_accessible()) {
pr_debug("%s: USB SAR CNTX registers are not accessible!\n",
__func__);
return -EBUSY;
}
/*
* SAR bits and clocks needs to be enabled
*/
clkdm_wakeup(l3init_clkdm);
pwrdm_enable_hdwr_sar(l3init_pwrdm);
clk_enable(usb_host_ck);
clk_enable(usb_tll_ck);
/* Save SAR BANK1 */
if (cpu_is_omap446x())
sar_save(ARRAY_SIZE(omap446x_sar_ram1_layout), SAR_BANK1_OFFSET,
omap446x_sar_ram1_layout);
else
sar_save(ARRAY_SIZE(omap443x_sar_ram1_layout), SAR_BANK1_OFFSET,
omap443x_sar_ram1_layout);
clk_disable(usb_host_ck);
clk_disable(usb_tll_ck);
pwrdm_disable_hdwr_sar(l3init_pwrdm);
clkdm_allow_idle(l3init_clkdm);
/* Save SAR BANK2 */
if (cpu_is_omap446x())
sar_save(ARRAY_SIZE(omap446x_sar_ram2_layout), SAR_BANK2_OFFSET,
omap446x_sar_ram2_layout);
else
sar_save(ARRAY_SIZE(omap443x_sar_ram2_layout), SAR_BANK2_OFFSET,
omap443x_sar_ram2_layout);
return 0;
}
int __init omap_devinit_temp_sensor(void)
{
if (!cpu_is_omap446x() && !cpu_is_omap447x())
return 0;
return omap_hwmod_for_each_by_class("thermal_sensor",
temp_sensor_dev_init, NULL);
}
static int __init omap_die_governor_init(void)
{
struct thermal_dev *thermal_fw;
omap_gov = kzalloc(sizeof(struct omap_die_governor), GFP_KERNEL);
if (!omap_gov) {
pr_err("%s:Cannot allocate memory\n", __func__);
return -ENOMEM;
}
thermal_fw = kzalloc(sizeof(struct thermal_dev), GFP_KERNEL);
if (thermal_fw) {
thermal_fw->name = "omap_ondie_governor";
thermal_fw->domain_name = "cpu";
thermal_fw->dev_ops = &omap_gov_ops;
thermal_governor_dev_register(thermal_fw);
therm_fw = thermal_fw;
} else {
pr_err("%s: Cannot allocate memory\n", __func__);
kfree(omap_gov);
return -ENOMEM;
}
if (cpu_is_omap446x()) {
omap_gov->gradient_slope = OMAP_GRADIENT_SLOPE_4460;
omap_gov->gradient_const = OMAP_GRADIENT_CONST_4460;
omap_gov->gradient_slope_w_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4460;
omap_gov->gradient_const_w_pcb = OMAP_GRADIENT_CONST_W_PCB_4460;
} else if (cpu_is_omap447x()) {
omap_gov->gradient_slope = OMAP_GRADIENT_SLOPE_4470;
omap_gov->gradient_const = OMAP_GRADIENT_CONST_4470;
omap_gov->gradient_slope_w_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4470;
omap_gov->gradient_const_w_pcb = OMAP_GRADIENT_CONST_W_PCB_4470;
} else {
omap_gov->gradient_slope = 0;
omap_gov->gradient_const = 0;
omap_gov->gradient_slope_w_pcb = 0;
omap_gov->gradient_const_w_pcb = 0;
}
/* Init delayed work to average on-die temperature */
INIT_DELAYED_WORK(&omap_gov->average_cpu_sensor_work,
average_cpu_sensor_delayed_work_fn);
INIT_DELAYED_WORK(&omap_gov->decrease_mpu_freq_work,
decrease_mpu_freq_fn);
omap_gov->average_period = NORMAL_TEMP_MONITORING_RATE;
omap_gov->decrease_mpu_freq_period = DECREASE_MPU_FREQ_PERIOD;
omap_gov->avg_is_valid = 0;
if (register_pm_notifier(&omap_die_pm_notifier))
pr_err("%s: omap_die pm registration failed!\n", __func__);
schedule_delayed_work(&omap_gov->average_cpu_sensor_work,
msecs_to_jiffies(0));
return 0;
}
static void sar_save(u32 nb_regs, u32 sar_bank, const u32 sar_layout_table[][4])
{
u32 reg_val, size, i, j;
void __iomem *reg_read_addr, *sar_wr_addr;
void *usb_sar_start;
void *usb_sar_end;
int usb_sar_table = 0;
usb_sar_start = sar_ram_base + sar_bank + USB_SAR_AREA_START;
usb_sar_end = sar_ram_base + sar_bank + USB_SAR_AREA_END;
/* 4460 USB SAR Registers are offset by 4 bytes */
if (cpu_is_omap446x()) {
usb_sar_start += 0x04;
usb_sar_end += 0x04;
}
if ((sar_layout_table == omap443x_sar_ram1_layout) ||
(sar_layout_table == omap446x_sar_ram1_layout))
usb_sar_table = 1;
for (i = 0; i < nb_regs; i++) {
if (omap4_sar_modules[(sar_layout_table[i][MODULE_ADDR_IDX])]) {
size = sar_layout_table[i][MODULE_NB_REGS_IDX];
reg_read_addr =
omap4_sar_modules[sar_layout_table[i]
[MODULE_ADDR_IDX]]
+ sar_layout_table[i][MODULE_OFFSET_IDX];
sar_wr_addr = sar_ram_base + sar_bank +
sar_layout_table[i][SAR_RAM_OFFSET_IDX];
for (j = 0; j < size; j++) {
reg_val = __raw_readl(reg_read_addr + j * 4);
if (usb_sar_table &&
sar_wr_addr+j*4 >= usb_sar_start &&
sar_wr_addr+j*4 < usb_sar_end) {
if (!sar_needs_ehci_saving) {
/* Use the stored version */
reg_val =
usb_sar_data
[(sar_wr_addr-usb_sar_start)/4
+ j].val;
} else {
/* Save the USB SAR register */
usb_sar_data
[(sar_wr_addr-usb_sar_start)/4
+ j].val = reg_val;
usb_sar_data
[(sar_wr_addr-usb_sar_start)/4
+ j].reg_addr = reg_read_addr;
}
}
__raw_writel(reg_val, sar_wr_addr + j * 4);
}
}
}
if (usb_sar_table)
sar_needs_ehci_saving = 0;
}
static void __init omap_tablet_init(void)
{
int status;
int package = OMAP_PACKAGE_CBS;
int tablet_rev = 0;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, NULL, package);
omap_emif_setup_device_details(&emif_devices, &emif_devices);
omap_board_config = tablet_config;
omap_board_config_size = ARRAY_SIZE(tablet_config);
tablet_rev = omap_init_board_version(0);
omap4_create_board_props();
omap4_audio_conf();
omap4_i2c_init();
tablet_touch_init();
tablet_camera_mux_init();
omap_dmm_init();
tablet_panel_init();
tablet_pmic_mux_init();
tablet_set_osc_timings();
tablet_button_init();
omap4_register_ion();
board_serial_init();
omap4_tablet_wifi_init();
omap4_twl6030_hsmmc_init(mmc);
tablet_sensor_init();
platform_add_devices(tablet4430_devices,
ARRAY_SIZE(tablet4430_devices));
wake_lock_init(&st_wk_lock, WAKE_LOCK_SUSPEND, "st_wake_lock");
omap4_ehci_ohci_init();
usb_musb_init(&musb_board_data);
status = omap_ethernet_init();
if (status) {
pr_err("Ethernet initialization failed: %d\n", status);
} else {
tablet_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
spi_register_board_info(tablet_spi_board_info,
ARRAY_SIZE(tablet_spi_board_info));
}
if (cpu_is_omap446x()) {
/* Vsel0 = gpio, vsel1 = gnd */
status = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
OMAP_PIN_OFF_OUTPUT_HIGH, -1);
if (status)
pr_err("TPS62361 initialization failed: %d\n", status);
}
omap_enable_smartreflex_on_init();
if (enable_suspend_off)
omap_pm_enable_off_mode();
}
static __init int omap4_ldo_trim_init(void)
{
u32 bgap_trimmed = 0;
/* Applicable only for OMAP4 */
if (!cpu_is_omap44xx())
return 0;
/*
* Some ES2.2 efuse values for BGAP and SLDO trim
* are not programmed. For these units
* 1. we can set overide mode for SLDO trim,
* and program the max multiplication factor, to ensure
* high enough voltage on SLDO output.
* 2. trim VDAC value for TV output as per recomendation
*/
if (omap_rev() >= CHIP_IS_OMAP4430ES2_2)
bgap_trimmed = omap_ctrl_readl(
OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP);
bgap_trimmed &= OMAP4_STD_FUSE_OPP_BGAP_MASK_LSB;
/* if not trimmed, we set force overide, insted of efuse. */
if (!bgap_trimmed)
bgap_trim_sw_overide = true;
/* If not already trimmed, use s/w override */
if (cpu_is_omap446x())
omap4460_mpu_dpll_trim_override();
/*
* Errata i684 (revision B)
* Impacts all OMAP4430ESx.y trimmed and untrimmed excluding units
* with with ProdID[51:50]=11
* OMAP4460/70 are not impacted.
*
* ProdID:
* 51 50
* 0 0 Incorrect trim, SW WA needed.
* 0 1 Fixed test program issue of overlapping of LPDDR & SmartIO
* efuse fields, SW WA needed for LPDDR.
* 1 1 New LPDDR trim formula to compensate for vertical vs horizontal
* cell layout. No overwrite required.
*/
if (cpu_is_omap443x()) {
u32 prod_id;
prod_id = omap_ctrl_readl(
OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
prod_id &= OMAP4_PROD_ID_I684_MASK;
if (prod_id != OMAP4_PROD_ID_I684_MASK)
ddr_io_trim_override = true;
}
return omap4_ldo_trim_configure();
}
void __init omap44xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap44xx);
if (cpu_is_omap443x())
pwrdm_register_pwrdms(powerdomains_omap443x);
if (cpu_is_omap446x())
pwrdm_register_pwrdms(powerdomains_omap446x);
pwrdm_complete_init();
}
void omap_temp_sensor_idle(int idle_state)
{
if (!cpu_is_omap446x() && !cpu_is_omap447x())
return;
if (idle_state)
omap_temp_sensor_disable(temp_sensor_pm);
else
omap_temp_sensor_enable(temp_sensor_pm);
}
void __init omap44xx_voltagedomains_init(void)
{
struct voltagedomain *voltdm;
int i;
omap4_voltdm_mpu.vp->vlimits->vddmax = OMAP4460_VP_MPU_VLIMITTO_VDDMAX;
omap4_voltdm_iva.vp->vlimits->vddmax = OMAP4460_VP_IVA_VLIMITTO_VDDMAX;
omap4_voltdm_core.vp->vlimits->vddmax = OMAP4460_VP_CORE_VLIMITTO_VDDMAX;
/*
* XXX Will depend on the process, validation, and binning
* for the currently-running IC
*/
if (cpu_is_omap443x()) {
struct setup_time_ramp_params *params =
omap4_vc_core.common->setup_time_params;
if (params) {
params->pre_scaler_to_sysclk_cycles =
pre_scaler_to_sysclk_cycles_443x;
}
omap4_vdd_mpu_info.volt_data = omap443x_vdd_mpu_volt_data;
omap4_vdd_iva_info.volt_data = omap443x_vdd_iva_volt_data;
omap4_vdd_core_info.volt_data = omap443x_vdd_core_volt_data;
omap4_vdd_mpu_info.dep_vdd_info = omap443x_vddmpu_dep_info;
omap4_vdd_iva_info.dep_vdd_info = omap443x_vddiva_dep_info;
omap4_voltdm_mpu.vp->vlimits->vddmax =
OMAP4430_VP_MPU_VLIMITTO_VDDMAX;
omap4_voltdm_iva.vp->vlimits->vddmax =
OMAP4430_VP_IVA_VLIMITTO_VDDMAX;
omap4_voltdm_core.vp->vlimits->vddmax =
OMAP4430_VP_CORE_VLIMITTO_VDDMAX;
} else if (cpu_is_omap446x()) {
omap4_vdd_mpu_info.volt_data = omap446x_vdd_mpu_volt_data;
omap4_vdd_iva_info.volt_data = omap446x_vdd_iva_volt_data;
omap4_vdd_core_info.volt_data = omap446x_vdd_core_volt_data;
omap4_vdd_mpu_info.dep_vdd_info = omap446x_vddmpu_dep_info;
omap4_vdd_iva_info.dep_vdd_info = omap446x_vddiva_dep_info;
} else if (cpu_is_omap447x()) {
omap4_vdd_mpu_info.volt_data = omap447x_vdd_mpu_volt_data;
omap4_vdd_iva_info.volt_data = omap447x_vdd_iva_volt_data;
omap4_vdd_core_info.volt_data = omap447x_vdd_core_volt_data;
omap4_vdd_mpu_info.dep_vdd_info = omap447x_vddmpu_dep_info;
omap4_vdd_iva_info.dep_vdd_info = omap447x_vddiva_dep_info;
} else {
return;
}
for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;
voltdm_init(voltagedomains_omap4);
};
/**
* omap4_sar_overwrite :
* This API overwrite some of the SAR locations as a special cases
* The register content to be saved can be the register value before
* going into OFF-mode or a value that is required on wake up. This means
* that the restored register value can be different from the last value
* of the register before going into OFF-mode
* - CM1 and CM2 configuration
* Bits 0 of the CM_SHADOW_FREQ_CONFIG1 regiser and the
* CM_SHADOW_FREQ_CONFIG2 register are self-clearing and must
* be set at restore time. Thus, these data must always be
* overwritten in the SAR RAM.
* - Because USBHOSTHS and USBTLL restore needs a particular
* sequencing, the software must overwrite data read from
* the following registers implied in phase2a and phase 2b
*/
void omap4_sar_overwrite(void)
{
u32 val = 0;
u32 offset = 0;
if (cpu_is_omap446x())
offset = 0x04;
/* Overwriting Phase1 data to be restored */
/* CM2 MEMIF_CLKTRCTRL = SW_WKUP, before FREQ UPDATE */
__raw_writel(0x2, sar_ram_base + SAR_BANK1_OFFSET + 0xd0);
/* CM1 CM_SHADOW_FREQ_CONFIG2, Enable FREQ UPDATE */
val = __raw_readl(OMAP4430_CM_SHADOW_FREQ_CONFIG2);
/*
* FIXME: Implement FREQ UPDATE for L#/M5 before enabling this
* val |= 1 << OMAP4430_FREQ_UPDATE_SHIFT;
*/
__raw_writel(val, sar_ram_base + SAR_BANK1_OFFSET + 0x100);
/* CM1 CM_SHADOW_FREQ_CONFIG1, Enable FREQ UPDATE */
val = __raw_readl(OMAP4430_CM_SHADOW_FREQ_CONFIG1);
val |= 1 << OMAP4430_FREQ_UPDATE_SHIFT;
val &= ~OMAP4430_DLL_OVERRIDE_MASK;
__raw_writel(val, sar_ram_base + SAR_BANK1_OFFSET + 0x104);
/* CM2 MEMIF_CLKTRCTRL = HW_AUTO, after FREQ UPDATE */
__raw_writel(0x3, sar_ram_base + SAR_BANK1_OFFSET + 0x124);
/* Overwriting Phase2a data to be restored */
/* CM_L3INIT_USB_HOST_CLKCTRL: SAR_MODE = 1, MODULEMODE = 2 */
__raw_writel(0x00000012,
sar_ram_base + SAR_BANK1_OFFSET + 0x2ec + offset);
/* CM_L3INIT_USB_TLL_CLKCTRL: SAR_MODE = 1, MODULEMODE = 1 */
__raw_writel(0x00000011,
sar_ram_base + SAR_BANK1_OFFSET + 0x2f0 + offset);
/* CM2 CM_SDMA_STATICDEP : Enable static depedency for SAR modules */
__raw_writel(0x000090e8,
sar_ram_base + SAR_BANK1_OFFSET + 0x2f4 + offset);
/* Overwriting Phase2b data to be restored */
/* CM_L3INIT_USB_HOST_CLKCTRL: SAR_MODE = 0, MODULEMODE = 0 */
val = __raw_readl(OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL);
val &= (OMAP4430_CLKSEL_UTMI_P1_MASK | OMAP4430_CLKSEL_UTMI_P2_MASK);
__raw_writel(val, sar_ram_base + SAR_BANK1_OFFSET + 0x91c + offset);
/* CM_L3INIT_USB_TLL_CLKCTRL: SAR_MODE = 0, MODULEMODE = 0 */
__raw_writel(0x0000000,
sar_ram_base + SAR_BANK1_OFFSET + 0x920 + offset);
/* CM2 CM_SDMA_STATICDEP : Clear the static depedency */
__raw_writel(0x00000040,
sar_ram_base + SAR_BANK1_OFFSET + 0x924 + offset);
/* readback to ensure data reaches to SAR RAM */
barrier();
val = __raw_readl(sar_ram_base + SAR_BANK1_OFFSET + 0x924 + offset);
}
static void omap_init_gpu(void)
{
struct omap_hwmod *oh;
struct omap_device *od;
int max_omap_gpu_hwmod_name_len = 16;
char oh_name[max_omap_gpu_hwmod_name_len];
int l;
struct gpu_platform_data *pdata;
char *name = "pvrsrvkm";
l = snprintf(oh_name, max_omap_gpu_hwmod_name_len,
"gpu");
WARN(l >= max_omap_gpu_hwmod_name_len,
"String buffer overflow in GPU device setup\n");
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("omap_init_gpu: Could not look up %s\n", oh_name);
return;
}
pdata = kzalloc(sizeof(struct gpu_platform_data),
GFP_KERNEL);
if (!pdata) {
pr_err("omap_init_gpu: Platform data memory allocation failed\n");
return;
}
#ifdef CONFIG_OMAP4_DPLL_CASCADING
pdata->device_scale = omap_device_scale_gpu;
#else
pdata->device_scale = omap_device_scale;
#endif
pdata->device_enable = omap_device_enable;
pdata->device_idle = omap_device_idle;
pdata->device_shutdown = omap_device_shutdown;
pdata->opp_get_opp_count = opp_get_opp_count;
pdata->opp_find_freq_ceil = opp_find_freq_ceil;
pdata->access_process_vm = access_process_vm;
pdata->ovfreqs = 0;
if (cpu_is_omap446x())
pdata->ovfreqs = 1;
od = omap_device_build(name, 0, oh, pdata,
sizeof(struct gpu_platform_data),
omap_gpu_latency, ARRAY_SIZE(omap_gpu_latency), 0);
WARN(IS_ERR(od), "Could not build omap_device for %s %s\n",
name, oh_name);
kfree(pdata);
}
void __init omap4_power_init(void)
{
/*
* VCORE3 & VMEM are not used in 4460. By register it to regulator
* framework will ensures that resources are disabled.
*/
if (cpu_is_omap446x()) {
twldata.vdd3 = &vcore3;
twldata.vmem = &vmem;
}
omap4_pmic_init("twl6030", &twldata);
}
int __init omap_devinit_temp_sensor(void)
{
if (!cpu_is_omap446x() && !cpu_is_omap443x())
return 0;
if (cpu_is_omap443x()) {
if (omap4_has_mpu_1_2ghz())
return omap_hwmod_for_each_by_class("bandgap",
temp_sensor_dev_init, NULL);
else
return 0;
} else
return omap_hwmod_for_each_by_class("thermal_sensor",
temp_sensor_dev_init, NULL);
}
static void omap_init_gpu(void)
{
struct omap_hwmod *oh;
struct platform_device *pd;
int max_omap_drm_hwmod_name_len = 16;
char oh_name[max_omap_drm_hwmod_name_len];
int l;
struct gpu_platform_data *pdata;
// char *name = "omapdrm_pvr";
char *name = "pvrsrvkm";
l = snprintf(oh_name, max_omap_drm_hwmod_name_len,
"gpu");
WARN(l >= max_omap_drm_hwmod_name_len,
"String buffer overflow in GPU device setup\n");
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("omap_init_gpu: Could not look up %s\n", oh_name);
return;
}
pdata = kzalloc(sizeof(struct gpu_platform_data),
GFP_KERNEL);
if (!pdata) {
pr_err("omap_init_gpu: Platform data memory allocation failed\n");
return;
}
pdata->device_scale = omap_device_scale;
pdata->device_enable = omap_device_enable;
pdata->device_idle = omap_device_idle;
pdata->device_shutdown = omap_device_shutdown;
pdata->ovfreqs = 0;
if (cpu_is_omap446x())
pdata->ovfreqs = 1;
pd = omap_device_build(name, 0, oh, pdata,
sizeof(struct gpu_platform_data),
omap_drm_latency, ARRAY_SIZE(omap_drm_latency), 0);
WARN(IS_ERR(pd), "Could not build omap_device for %s %s\n",
name, oh_name);
kfree(pdata);
platform_device_register(&omap_omaplfb_device);
}
/*
* Continue initialise the wakeupgen initialization after sar
* is initialized
*/
void __init omap_wakeupgen_init_finish(void)
{
int i;
unsigned int max_spi_reg;
/*
* Find out how many interrupts are supported.
* OMAP4 supports max of 128 SPIs where as GIC can support
* up to 1020 interrupt sources. On OMAP4, maximum SPIs are
* fused in DIST_CTR bit-fields as 128. Hence the code is safe
* from reserved register writes since its well within 1020.
*/
max_spi_reg = gic_readl(GIC_DIST_CTR, 0) & 0x1f;
/*
* Set CPU0 GIC backup flag permanently for omap4460/70 GP,
* this is needed because of the ROM code bug that breaks
* GIC during wakeup from device off. This errata fix also
* clears the GIC save area during init to prevent restoring
* garbage to the GIC.
*/
if ((cpu_is_omap446x() || cpu_is_omap447x()) &&
omap_type() == OMAP2_DEVICE_TYPE_GP)
pm44xx_errata |= PM_OMAP4_ROM_CPU1_BACKUP_ERRATUM_xxx;
if (cpu_is_omap44xx() && (omap_type() == OMAP2_DEVICE_TYPE_GP)) {
sar_base = omap4_get_sar_ram_base();
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_CPU1_BACKUP_ERRATUM_xxx))
for (i = SAR_BACKUP_STATUS_OFFSET;
i < WAKEUPGENENB_OFFSET_CPU0; i += 4)
sar_writel(0, i, 0);
sar_writel(GIC_ISR_NON_SECURE, SAR_ICDISR_CPU0_OFFSET, 0);
sar_writel(GIC_ISR_NON_SECURE, SAR_ICDISR_CPU1_OFFSET, 0);
for (i = 0; i < max_spi_reg; i++)
sar_writel(GIC_ISR_NON_SECURE, SAR_ICDISR_SPI_OFFSET,
i);
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_CPU1_BACKUP_ERRATUM_xxx))
__raw_writel(SAR_BACKUP_STATUS_GIC_CPU0,
sar_base + SAR_BACKUP_STATUS_OFFSET);
} else {
l3_main_3_oh = omap_hwmod_lookup("l3_main_3");
if (!l3_main_3_oh)
pr_err("%s: failed to get l3_main_3_oh\n", __func__);
}
}
static void __init omap_4430sdp_init(void)
{
int status;
int package = OMAP_PACKAGE_CBS;
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
omap4_mux_init(board_mux, NULL, package);
omap_emif_setup_device_details(&emif_devices, &emif_devices);
omap_board_config = sdp4430_config;
omap_board_config_size = ARRAY_SIZE(sdp4430_config);
omap4_i2c_init();
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
board_serial_init();
omap4_twl6030_hsmmc_init(mmc);
usb_musb_init(&musb_board_data);
status = omap_ethernet_init();
if (status) {
pr_err("Ethernet initialization failed: %d\n", status);
} else {
sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
spi_register_board_info(sdp4430_spi_board_info,
ARRAY_SIZE(sdp4430_spi_board_info));
}
status = omap4_keyboard_init(&sdp4430_keypad_data);
if (status)
pr_err("Keypad initialization failed: %d\n", status);
omap_dmm_init();
omap_4430sdp_display_init();
if (cpu_is_omap446x()) {
/* Vsel0 = gpio, vsel1 = gnd */
status = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
OMAP_PIN_OFF_OUTPUT_HIGH, -1);
if (status)
pr_err("TPS62361 initialization failed: %d\n", status);
}
}
static ssize_t omap4_soc_rbb_trimmed(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
int trimmed = 1;
int reg = 0;
if (cpu_is_omap446x()) {
/* read eFuse register here */
reg = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1);
trimmed = reg & (1 << 20);
pr_info("%s:RBB is %s set\n", __func__, trimmed ? "" : "not");
return sprintf(buf, "%s\n", trimmed ? "true" : "false");
}
return sprintf(buf, "%s\n", "Not Available");
}
static int __init omap4_i2c_init(void)
{
omap_i2c_hwspinlock_init(1, 0, &sdp4430_i2c_1_bus_pdata);
omap_i2c_hwspinlock_init(2, 1, &sdp4430_i2c_2_bus_pdata);
omap_i2c_hwspinlock_init(3, 2, &sdp4430_i2c_3_bus_pdata);
omap_i2c_hwspinlock_init(4, 3, &sdp4430_i2c_4_bus_pdata);
omap_register_i2c_bus_board_data(1, &sdp4430_i2c_1_bus_pdata);
omap_register_i2c_bus_board_data(2, &sdp4430_i2c_2_bus_pdata);
omap_register_i2c_bus_board_data(3, &sdp4430_i2c_3_bus_pdata);
omap_register_i2c_bus_board_data(4, &sdp4430_i2c_4_bus_pdata);
/*
* VCORE3 & VMEM are not used in 4460. By register it to regulator
* framework will ensures that resources are disabled.
*/
if (cpu_is_omap446x()) {
tablet_twldata.vdd3 = &tablet_vcore3;
tablet_twldata.vmem = &tablet_vmem;
}
omap4_pmic_init("twl6030", &tablet_twldata);
i2c_register_board_info(1, sdp4430_i2c_boardinfo,
ARRAY_SIZE(sdp4430_i2c_boardinfo));
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, tablet_i2c_3_boardinfo,
ARRAY_SIZE(tablet_i2c_3_boardinfo));
omap_register_i2c_bus(4, 400, NULL, 0);
omap2_i2c_pullup(3, I2C_PULLUP_STD_860_OM_FAST_500_OM);
/*
* This will allow unused regulator to be shutdown. This flag
* should be set in the board file. Before regulators are registered.
*/
regulator_has_full_constraints();
/*
* Drive MSECURE high for TWL6030 write access.
*/
omap_mux_init_signal("fref_clk0_out.gpio_wk6", OMAP_PIN_OUTPUT);
gpio_request(6, "msecure");
gpio_direction_output(6, 1);
return 0;
}
static void __init tablet_camera_mux_init(void)
{
u32 r = 0;
/* Enable CSI22 pads for 4460 and 4470*/
if ((cpu_is_omap446x() || cpu_is_omap447x()) &&
(omap_get_board_version() >= OMAP4_TABLET_2_0)) {
r = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX);
r |= (0x7 << OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT);
omap4_ctrl_pad_writel(r,
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX);
omap_mux_init_signal("csi22_dx2.csi22_dx2",
OMAP_PIN_INPUT | OMAP_MUX_MODE0);
omap_mux_init_signal("csi22_dy2.csi22_dy2",
OMAP_PIN_INPUT | OMAP_MUX_MODE0);
}
}
static void __init omap4_panda_display_init(void)
{
omap_display_init(&omap4_panda_dss_data);
/*
* OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
* later have external pull up on the HDMI I2C lines
*/
if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
else
omap_hdmi_init(0);
omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
}