void
platform_mp_start_ap(void)
{
bus_space_handle_t ocm_handle;
/* Map in magic location to give entry address to CPU1. */
if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
0, &ocm_handle) != 0)
panic("platform_mp_start_ap: Couldn't map OCM\n");
/* Write start address for CPU1. */
bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
pmap_kextract((vm_offset_t)mpentry));
/*
* The SCU is enabled by the BOOTROM but I think the second CPU doesn't
* turn on filtering until after the wake-up below. I think that's why
* things don't work if I don't put these cache ops here. Also, the
* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
* needs a write-back too.
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Wake up CPU1. */
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
}
/* Initialize and fire up non-boot processors */
void
cpu_mp_start(void)
{
int error, i;
mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
/* Reserve memory for application processors */
for(i = 0; i < (mp_ncpus - 1); i++)
dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
M_WAITOK | M_ZERO);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
cpu_idcache_wbinv_all();
/* Initialize boot code and start up processors */
platform_mp_start_ap();
/* Check if ap's started properly */
error = check_ap();
if (error)
printf("WARNING: Some AP's failed to start\n");
else
for (i = 1; i < mp_ncpus; i++)
CPU_SET(i, &all_cpus);
}
int
elf_cpu_load_file(linker_file_t lf __unused)
{
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
cpu_tlb_flushID();
return (0);
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu, rst, ram;
int reg;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
RSTMGR_SIZE, 0, &rst) != 0)
panic("Couldn't map the reset manager (RSTMGR)\n");
if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
RAM_SIZE, 0, &ram) != 0)
panic("Couldn't map the first physram page\n");
/* Invalidate SCU cache tags */
bus_space_write_4(fdtbus_bs_tag, scu,
SCU_INV_TAGS_REG, 0x0000ffff);
/*
* Erratum ARM/MP: 764369 (problems with cache maintenance).
* Setting the "disable-migratory bit" in the undocumented SCU
* Diagnostic Control Register helps work around the problem.
*/
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
reg |= (SCU_DIAG_DISABLE_MIGBIT);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
/* Put CPU1 to reset state */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1);
/* Enable the SCU, then clean the cache on this core */
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
reg |= (SCU_CONTROL_ENABLE);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
/* Set up trampoline code */
mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
(uint32_t *)&socfpga_trampoline, 8);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Put CPU1 out from reset */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
}
void
dumpsys_wbinv_all(void)
{
/*
* Make sure we write coherent data. Note that in the SMP case this
* only operates on the L1 cache of the current CPU, but all other CPUs
* have already been stopped, and their flush/invalidate was done as
* part of stopping.
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
#ifdef __XSCALE__
xscale_cache_clean_minidata();
#endif
}
void
platform_mp_start_ap(void)
{
bus_addr_t scu_addr;
if (bus_space_map(fdtbus_bs_tag, 0x48240000, 0x1000, 0, &scu_addr) != 0)
panic("Couldn't map the SCU\n");
/* Enable the SCU */
*(volatile unsigned int *)scu_addr |= 1;
//*(volatile unsigned int *)(scu_addr + 0x30) |= 1;
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0);
ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu_addr, 0x1000);
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu_handle;
bus_space_handle_t ocm_handle;
uint32_t scu_ctrl;
/* Map in SCU control register. */
if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
0, &scu_handle) != 0)
panic("platform_mp_start_ap: Couldn't map SCU config reg\n");
/* Set SCU enable bit. */
scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
scu_ctrl |= SCU_CONTROL_ENABLE;
bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
/* Map in magic location to give entry address to CPU1. */
if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
0, &ocm_handle) != 0)
panic("platform_mp_start_ap: Couldn't map OCM\n");
/* Write start address for CPU1. */
bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
pmap_kextract((vm_offset_t)mpentry));
bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
/*
* The SCU is enabled above but I think the second CPU doesn't
* turn on filtering until after the wake-up below. I think that's why
* things don't work if I don't put these cache ops here. Also, the
* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
* needs a write-back too.
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Wake up CPU1. */
armv7_sev();
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu;
bus_space_handle_t imem;
bus_space_handle_t pmu;
uint32_t val;
int i;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
panic("Could not map the SCU");
if (bus_space_map(fdtbus_bs_tag, IMEM_PHYSBASE,
IMEM_SIZE, 0, &imem) != 0)
panic("Could not map the IMEM");
if (bus_space_map(fdtbus_bs_tag, PMU_PHYSBASE, PMU_SIZE, 0, &pmu) != 0)
panic("Could not map the PMU");
/*
* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
* the bits for cores that are not present.
*/
bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
/* Make sure all cores except the first are off */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
for (i = 1; i < mp_ncpus; i++)
val |= 1 << i;
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
/* Enable SCU power domain */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
val &= ~PMU_PWRDN_SCU;
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
/* Enable SCU */
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
/*
* Cores will execute the code which resides at the start of
* the on-chip bootram/sram after power-on. This sram region
* should be reserved and the trampoline code that directs
* the core to the real startup code in ram should be copied
* into this sram region.
*
* First set boot function for the sram code.
*/
mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
/* Copy trampoline to sram, that runs during startup of the core */
bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
(uint32_t *)&rk30xx_boot2, 8);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Start all cores */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
for (i = 1; i < mp_ncpus; i++)
val &= ~(1 << i);
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE);
bus_space_unmap(fdtbus_bs_tag, pmu, PMU_SIZE);
}
