void
dec_3maxplus_init(void)
{
uint32_t prodtype;
platform.iobus = "tcbus";
platform.bus_reset = dec_3maxplus_bus_reset;
platform.cons_init = dec_3maxplus_cons_init;
platform.iointr = dec_3maxplus_intr;
platform.intr_establish = dec_3maxplus_intr_establish;
platform.memsize = memsize_bitmap;
/* 3MAX+ has IOASIC free-running high resolution timer */
platform.tc_init = dec_3maxplus_tc_init;
/* clear any memory errors */
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
kn03_wbflush();
ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
ipl_sr_map = dec_3maxplus_ipl_sr_map;
/* calibrate cpu_mhz value */
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
*(volatile uint32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(volatile uint32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
#if 0
*(volatile uint32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(volatile uint32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
*(volatile uint32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
#endif
/* XXX hard-reset LANCE */
*(volatile uint32_t *)(ioasic_base + IOASIC_CSR) |= 0x100;
/* sanitize interrupt mask */
kn03_tc3_imask = KN03_INTR_PSWARN;
*(volatile uint32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask;
kn03_wbflush();
prodtype = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
prodtype &= KN03_INTR_PROD_JUMPER;
/* the bit persists even if INTR register is assigned value 0 */
if (prodtype)
cpu_setmodel("DECstation 5000/%s (3MAXPLUS)",
(CPUISMIPS3) ? "260" : "240");
else
cpu_setmodel("DECsystem 5900%s (3MAXPLUS)",
(CPUISMIPS3) ? "-260" : "");
}
void
identifycpu(void)
{
extern int cputype;
const char *model, *fpu;
switch (cputype) {
case CPU_68030:
model ="LUNA-I";
switch (fputype) {
case FPU_68881:
fpu = "MC68881";
break;
case FPU_68882:
fpu = "MC68882";
break;
case FPU_NONE:
fpu = "no";
break;
default:
fpu = "unknown";
break;
}
cpu_setmodel("%s (MC68030 CPU+MMU, %s FPU)", model, fpu);
machtype = LUNA_I;
/* 20MHz 68030 */
cpuspeed = 20;
delay_divisor = 102;
hz = 60;
break;
#if defined(M68040)
case CPU_68040:
model ="LUNA-II";
cpu_setmodel(
"%s (MC68040 CPU+MMU+FPU, 4k on-chip physical I/D caches)",
model);
machtype = LUNA_II;
/* 25MHz 68040 */
cpuspeed = 25;
delay_divisor = 30;
/* hz = 100 on LUNA-II */
break;
#endif
default:
panic("unknown CPU type");
}
printf("%s\n", cpu_getmodel());
}
/*
* cpu_startup: allocate memory for variable-sized tables,
* initialize CPU, and do autoconfiguration.
*/
void
cpu_startup(void)
{
vaddr_t minaddr, maxaddr;
#ifdef DEBUG
extern int pmapdebug;
int opmapdebug = pmapdebug;
pmapdebug = 0;
#endif
cpu_setmodel("FIC8234");
if (fputype != FPU_NONE)
m68k_make_fpu_idle_frame();
/*
* Good {morning,afternoon,evening,night}.
*/
printf("%s%s", copyright, version);
identifycpu();
printf("real mem = %d\n", ctob(physmem));
minaddr = 0;
/*
* Allocate a submap for physio
*/
phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
VM_PHYS_SIZE, 0, false, NULL);
#ifdef DEBUG
pmapdebug = opmapdebug;
#endif
printf("avail mem = %ld\n", ptoa(uvmexp.free));
}
void
xs_bee3_init(void)
{
platform.iobus = "baseboard";
platform.bus_reset = noop;
platform.cons_init = xs_bee3_cons_init;
platform.iointr = emips_aic_intr;
platform.intr_establish = emips_intr_establish;
platform.memsize = memsize_pmt;
/* no high resolution timer available (actually we do?) */
/* calibrate cpu_mhz value */
//cpu_mhz = 10;
cpuspeed = 8; /* xxx */
cpu_setmodel("BeSquare BEE3 (eMIPS)");
ipl_sr_map = xs_bee3_ipl_sr_map;
}
void
dec_maxine_init(void)
{
platform.iobus = "tcbus";
platform.bus_reset = dec_maxine_bus_reset;
platform.cons_init = dec_maxine_cons_init;
platform.iointr = dec_maxine_intr;
platform.intr_establish = dec_maxine_intr_establish;
platform.memsize = memsize_bitmap;
platform.tc_init = dec_maxine_tc_init;
/* MAXINE has 1 microsec. free-running high resolution timer */
/* clear any memory errors */
*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
kn02ca_wbflush();
ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
ipl_sr_map = dec_maxine_ipl_sr_map;
/* calibrate cpu_mhz value */
mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
*(volatile uint32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
*(volatile uint32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
#if 0
*(volatile uint32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
*(volatile uint32_t *)(ioasic_base + IOASIC_DTOP_DECODE) = 10;
*(volatile uint32_t *)(ioasic_base + IOASIC_FLOPPY_DECODE) = 13;
*(volatile uint32_t *)(ioasic_base + IOASIC_CSR) = 0x00001fc1;
#endif
/* sanitize interrupt mask */
xine_tc3_imask = 0;
*(volatile uint32_t *)(ioasic_base + IOASIC_INTR) = 0;
*(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask;
kn02ca_wbflush();
cpu_setmodel("Personal DECstation 5000/%d (MAXINE)", mips_options.mips_cpu_mhz);
}
/*
* Do all the stuff that locore normally does before calling main().
*/
void
mach_init(int32_t memsize32, u_int bim, int32_t bip32)
{
intptr_t memsize = (int32_t)memsize32;
char *kernend;
char *bip = (char *)(intptr_t)(int32_t)bip32;
u_long first, last;
extern char edata[], end[];
const char *bi_msg;
#if NKSYMS || defined(DDB) || defined(MODULAR)
char *ssym = 0;
struct btinfo_symtab *bi_syms;
#endif
struct btinfo_howto *bi_howto;
/*
* Clear the BSS segment (if needed).
*/
if (memcmp(((Elf_Ehdr *)end)->e_ident, ELFMAG, SELFMAG) == 0 &&
((Elf_Ehdr *)end)->e_ident[EI_CLASS] == ELFCLASS) {
esym = end;
#if NKSYMS || defined(DDB) || defined(MODULAR)
esym += ((Elf_Ehdr *)end)->e_entry;
#endif
kernend = (char *)mips_round_page(esym);
/*
* We don't have to clear BSS here
* since our bootloader already does it.
*/
#if 0
memset(edata, 0, end - edata);
#endif
} else {
kernend = (void *)mips_round_page(end);
/*
* No symbol table, so assume we are loaded by
* the firmware directly with "bfd" command.
* The firmware loader doesn't clear BSS of
* a loaded kernel, so do it here.
*/
memset(edata, 0, kernend - edata);
}
/*
* Copy exception-dispatch code down to exception vector.
* Initialize locore-function vector.
* Clear out the I and D caches.
*/
mips_vector_init(NULL, false);
/* Check for valid bootinfo passed from bootstrap */
if (bim == BOOTINFO_MAGIC) {
struct btinfo_magic *bi_magic;
bootinfo = bip;
bi_magic = lookup_bootinfo(BTINFO_MAGIC);
if (bi_magic == NULL) {
bi_msg = "missing bootinfo structure";
bim = (uintptr_t)bip;
} else if (bi_magic->magic != BOOTINFO_MAGIC) {
bi_msg = "invalid bootinfo structure";
bim = bi_magic->magic;
} else
bi_msg = NULL;
} else {
bi_msg = "invalid bootinfo (standalone boot?)";
}
#if NKSYMS || defined(DDB) || defined(MODULAR)
bi_syms = lookup_bootinfo(BTINFO_SYMTAB);
/* Load symbol table if present */
if (bi_syms != NULL) {
ssym = (void *)(intptr_t)bi_syms->ssym;
esym = (void *)(intptr_t)bi_syms->esym;
kernend = (void *)mips_round_page(esym);
}
#endif
bi_howto = lookup_bootinfo(BTINFO_HOWTO);
if (bi_howto != NULL)
boothowto = bi_howto->bi_howto;
cobalt_id = read_board_id();
if (cobalt_id >= COBALT_MODELS || cobalt_model[cobalt_id] == NULL)
cpu_setmodel("Cobalt unknown model (board ID %u)",
cobalt_id);
else
cpu_setmodel("%s", cobalt_model[cobalt_id]);
switch (cobalt_id) {
case COBALT_ID_QUBE2700:
case COBALT_ID_RAQ:
cpuspeed = 150; /* MHz */
break;
case COBALT_ID_QUBE2:
case COBALT_ID_RAQ2:
cpuspeed = 250; /* MHz */
break;
default:
/* assume the fastest, so that delay(9) works */
cpuspeed = 250;
break;
}
curcpu()->ci_cpu_freq = cpuspeed * 1000 * 1000;
curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
curcpu()->ci_divisor_delay =
((curcpu()->ci_cpu_freq + (1000000 / 2)) / 1000000);
/* all models have Rm5200, which is CPU_MIPS_DOUBLE_COUNT */
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
physmem = btoc(memsize - MIPS_KSEG0_START);
consinit();
KASSERT(&lwp0 == curlwp);
if (bi_msg != NULL)
printf("%s: magic=%#x bip=%p\n", bi_msg, bim, bip);
uvm_setpagesize();
/*
* The boot command is passed in the top 512 bytes,
* so don't clobber that.
*/
mem_clusters[0].start = 0;
mem_clusters[0].size = ctob(physmem) - 512;
mem_cluster_cnt = 1;
memcpy(bootstring, (char *)(memsize - 512), 512);
memset((char *)(memsize - 512), 0, 512);
bootstring[511] = '\0';
decode_bootstring();
#if NKSYMS || defined(DDB) || defined(MODULAR)
/* init symbols if present */
if ((bi_syms != NULL) && (esym != NULL))
ksyms_addsyms_elf(esym - ssym, ssym, esym);
#endif
KASSERT(&lwp0 == curlwp);
#ifdef DDB
if (boothowto & RB_KDB)
Debugger();
#endif
#ifdef KGDB
if (boothowto & RB_KDB)
kgdb_connect(0);
#endif
/*
* Load the rest of the available pages into the VM system.
*/
first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
last = mem_clusters[0].start + mem_clusters[0].size;
uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
VM_FREELIST_DEFAULT);
/*
* Initialize error message buffer (at end of core).
*/
mips_init_msgbuf();
pmap_bootstrap();
/*
* Allocate space for proc0's USPACE.
*/
mips_init_lwp0_uarea();
}
void
mach_init(void)
{
void *kernend;
uint32_t memsize;
extern char edata[], end[]; /* XXX */
/* clear the BSS segment */
kernend = (void *)mips_round_page(end);
memset(edata, 0, (char *)kernend - edata);
/* setup early console */
ingenic_putchar_init();
/* set CPU model info for sysctl_hw */
cpu_setmodel("Ingenic XBurst");
mips_vector_init(NULL, false);
cal_timer();
uvm_setpagesize();
/*
* Look at arguments passed to us and compute boothowto.
*/
boothowto = RB_AUTOBOOT;
#ifdef KADB
boothowto |= RB_KDB;
#endif
/*
* Determine the memory size.
*
* Note: Reserve the first page! That's where the trap
* vectors are located.
*/
memsize = 0x40000000;
printf("Memory size: 0x%08x\n", memsize);
physmem = btoc(memsize);
/*
* memory is at 0x20000000 with first 256MB mirrored to 0x00000000 so
* we can see them through KSEG*
* assume 1GB for now, the SoC can theoretically support up to 3GB
*/
mem_clusters[0].start = PAGE_SIZE;
mem_clusters[0].size = 0x10000000 - PAGE_SIZE;
mem_clusters[1].start = 0x30000000;
mem_clusters[1].size = 0x30000000;
mem_cluster_cnt = 2;
/*
* Load the available pages into the VM system.
*/
mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
mem_clusters, mem_cluster_cnt, NULL, 0);
/*
* Initialize message buffer (at end of core).
*/
mips_init_msgbuf();
/*
* Initialize the virtual memory system.
*/
pmap_bootstrap();
/*
* Allocate uarea page for lwp0 and set it.
*/
mips_init_lwp0_uarea();
#ifdef MULTIPROCESSOR
mutex_init(&ingenic_ipi_lock, MUTEX_DEFAULT, IPL_HIGH);
mips_locoresw.lsw_send_ipi = ingenic_send_ipi;
mips_locoresw.lsw_cpu_init = ingenic_cpu_init;
#endif
apbus_init();
/*
* Initialize debuggers, and break into them, if appropriate.
*/
#ifdef DDB
if (boothowto & RB_KDB)
Debugger();
#endif
}
void
mach_init(void)
{
vaddr_t kernend;
psize_t memsize;
extern char kernel_text[];
extern char edata[], end[]; /* From Linker */
/* clear the BSS segment */
kernend = mips_round_page(end);
memset(edata, 0, kernend - (vaddr_t)edata);
#ifdef RALINK_CONSOLE_EARLY
/*
* set up early console
* cannot printf until sometime (?) in mips_vector_init
* meanwhile can use the ra_console_putc primitive if necessary
*/
ralink_console_early();
#endif
/* set CPU model info for sysctl_hw */
uint32_t tmp1, tmp2;
char id1[5], id2[5];
tmp1 = sysctl_read(RA_SYSCTL_ID0);
memcpy(id1, &tmp1, sizeof(tmp1));
tmp2 = sysctl_read(RA_SYSCTL_ID1);
memcpy(id2, &tmp2, sizeof(tmp2));
id2[4] = id1[4] = '\0';
if (id2[2] == ' ') {
id2[2] = '\0';
} else if (id2[3] == ' ') {
id2[3] = '\0';
} else {
id2[4] = '\0';
}
cpu_setmodel("%s%s", id1, id2);
/*
* Set up the exception vectors and CPU-specific function
* vectors early on. We need the wbflush() vector set up
* before comcnattach() is called (or at least before the
* first printf() after that is called).
* Sets up mips_cpu_flags that may be queried by other
* functions called during startup.
* Also clears the I+D caches.
*/
mips_vector_init(NULL, false);
/*
* Calibrate timers.
*/
cal_timer();
/*
* Set the VM page size.
*/
uvm_setpagesize();
/*
* Look at arguments passed to us and compute boothowto.
*/
boothowto = RB_AUTOBOOT;
#ifdef KADB
boothowto |= RB_KDB;
#endif
/*
* Determine the memory size.
*/
#if defined(MT7620)
memsize = 128 << 20;
#else
memsize = *(volatile uint32_t *)
MIPS_PHYS_TO_KSEG1(RA_SYSCTL_BASE + RA_SYSCTL_CFG0);
memsize = __SHIFTOUT(memsize, SYSCTL_CFG0_DRAM_SIZE);
if (__predict_false(memsize == 0)) {
memsize = 2 << 20;
} else {
memsize = 4 << (20 + memsize);
}
#endif
physmem = btoc(memsize);
mem_clusters[mem_cluster_cnt].start = 0;
mem_clusters[mem_cluster_cnt].size = memsize;
mem_cluster_cnt++;
/*
* Load the memory into the VM system
*/
mips_page_physload((vaddr_t)kernel_text, kernend,
mem_clusters, mem_cluster_cnt,
NULL, 0);
/*
* Initialize message buffer (at end of core).
*/
mips_init_msgbuf();
/*
* Initialize the virtual memory system.
*/
pmap_bootstrap();
/*
* Init mapping for u page(s) for proc0.
*/
mips_init_lwp0_uarea();
/*
* Initialize busses.
*/
ra_bus_init();
#ifdef DDB
if (boothowto & RB_KDB)
Debugger();
#endif
}
void
mach_init(void)
{
void *kernend;
uint32_t memsize;
extern char edata[], end[]; /* XXX */
/* clear the BSS segment */
kernend = (void *)mips_round_page(end);
memset(edata, 0, (char *)kernend - edata);
/* setup early console */
ingenic_putchar_init();
/* set CPU model info for sysctl_hw */
cpu_setmodel("Ingenic XBurst");
mips_vector_init(NULL, false);
cal_timer();
uvm_setpagesize();
/*
* Look at arguments passed to us and compute boothowto.
*/
boothowto = RB_AUTOBOOT;
#ifdef KADB
boothowto |= RB_KDB;
#endif
/*
* Determine the memory size.
*
* Note: Reserve the first page! That's where the trap
* vectors are located.
*/
memsize = 0x40000000;
printf("Memory size: 0x%08x\n", memsize);
physmem = btoc(memsize);
/* XXX this is CI20 specific */
mem_clusters[0].start = PAGE_SIZE;
mem_clusters[0].size = 0x10000000 - PAGE_SIZE;
mem_clusters[1].start = 0x30000000;
mem_clusters[1].size = 0x30000000;
mem_cluster_cnt = 2;
/*
* Load the available pages into the VM system.
*/
mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
mem_clusters, mem_cluster_cnt, NULL, 0);
/*
* Initialize message buffer (at end of core).
*/
mips_init_msgbuf();
/*
* Initialize the virtual memory system.
*/
pmap_bootstrap();
/*
* Allocate uarea page for lwp0 and set it.
*/
mips_init_lwp0_uarea();
apbus_init();
/*
* Initialize debuggers, and break into them, if appropriate.
*/
#ifdef DDB
if (boothowto & RB_KDB)
Debugger();
#endif
}
